diff --git a/lib/cretonne/src/isa/arm32/mod.rs b/lib/cretonne/src/isa/arm32/mod.rs
index 63f6293516..63e9516a13 100644
--- a/lib/cretonne/src/isa/arm32/mod.rs
+++ b/lib/cretonne/src/isa/arm32/mod.rs
@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
-        &registers::INFO
+    fn register_info(&self) -> RegInfo {
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
diff --git a/lib/cretonne/src/isa/arm64/mod.rs b/lib/cretonne/src/isa/arm64/mod.rs
index 2c2b98437b..4d00b1d49e 100644
--- a/lib/cretonne/src/isa/arm64/mod.rs
+++ b/lib/cretonne/src/isa/arm64/mod.rs
@@ -42,8 +42,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
-        &registers::INFO
+    fn register_info(&self) -> RegInfo {
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
diff --git a/lib/cretonne/src/isa/intel/mod.rs b/lib/cretonne/src/isa/intel/mod.rs
index 13b77e1dd2..533c264e3d 100644
--- a/lib/cretonne/src/isa/intel/mod.rs
+++ b/lib/cretonne/src/isa/intel/mod.rs
@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
-        &registers::INFO
+    fn register_info(&self) -> RegInfo {
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
diff --git a/lib/cretonne/src/isa/mod.rs b/lib/cretonne/src/isa/mod.rs
index ee33bb4c47..af689a3947 100644
--- a/lib/cretonne/src/isa/mod.rs
+++ b/lib/cretonne/src/isa/mod.rs
@@ -132,7 +132,7 @@ pub trait TargetIsa {
     fn flags(&self) -> &settings::Flags;
 
     /// Get a data structure describing the registers in this ISA.
-    fn register_info(&self) -> &RegInfo;
+    fn register_info(&self) -> RegInfo;
 
     /// Encode an instruction after determining it is legal.
     ///
diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 5e89110284..588fc0b14d 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -168,6 +168,7 @@ impl From<RegClass> for RegClassIndex {
 ///
 /// The `RegUnit` data structure collects all relevant static information about the registers in an
 /// ISA.
+#[derive(Clone)]
 pub struct RegInfo {
     /// All register banks, ordered by their `first_unit`. The register banks are disjoint, but
     /// there may be holes of unused register unit numbers between banks due to alignment.
diff --git a/lib/cretonne/src/isa/riscv/mod.rs b/lib/cretonne/src/isa/riscv/mod.rs
index 34b2a43c99..b997316733 100644
--- a/lib/cretonne/src/isa/riscv/mod.rs
+++ b/lib/cretonne/src/isa/riscv/mod.rs
@@ -49,8 +49,8 @@ impl TargetIsa for Isa {
         &self.shared_flags
     }
 
-    fn register_info(&self) -> &RegInfo {
-        &registers::INFO
+    fn register_info(&self) -> RegInfo {
+        registers::INFO.clone()
     }
 
     fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
diff --git a/lib/cretonne/src/regalloc/liveness.rs b/lib/cretonne/src/regalloc/liveness.rs
index e34ceda915..da4b2568f9 100644
--- a/lib/cretonne/src/regalloc/liveness.rs
+++ b/lib/cretonne/src/regalloc/liveness.rs
@@ -324,7 +324,7 @@ impl Liveness {
                     // resolved by the coloring algorithm, and ABI constraints require specific
                     // registers or stack slots which the affinities don't model anyway.
                     if let Some(constraint) = operand_constraints.next() {
-                        lr.affinity.merge(constraint, reg_info);
+                        lr.affinity.merge(constraint, &reg_info);
                     }
                 });
             }