Generate register bank descriptions.

Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.

lib/cretonne/meta/build.py

@@ -11,6 +11,7 @@ import gen_settings
 import gen_build_deps
 import gen_encoding
 import gen_legalizer
+import gen_registers
 
 parser = argparse.ArgumentParser(description='Generate sources for Cretonne.')
 parser.add_argument('--out-dir', help='set output directory')
@@ -25,4 +26,5 @@ gen_instr.generate(isas, out_dir)
 gen_settings.generate(isas, out_dir)
 gen_encoding.generate(isas, out_dir)
 gen_legalizer.generate(isas, out_dir)
+gen_registers.generate(isas, out_dir)
 gen_build_deps.generate()

lib/cretonne/meta/gen_registers.py

@@ -0,0 +1,51 @@
+"""
+Generate register bank descriptions for each ISA.
+"""
+
+from __future__ import absolute_import
+import srcgen
+
+try:
+    from typing import Sequence  # noqa
+    from cdsl.isa import TargetISA  # noqa
+    from cdsl.registers import RegBank  # noqa
+except ImportError:
+    pass
+
+
+def gen_regbank(regbank, fmt):
+    # type: (RegBank, srcgen.Formatter) -> None
+    """
+    Emit a static data definition for regbank.
+    """
+    with fmt.indented(
+            'RegBank {{'.format(regbank.name), '},'):
+        fmt.line('name: "{}",'.format(regbank.name))
+        fmt.line('first_unit: {},'.format(regbank.first_unit))
+        fmt.line('units: {},'.format(regbank.units))
+        fmt.line(
+                'names: &[{}],'
+                .format(', '.join('"{}"'.format(n) for n in regbank.names)))
+        fmt.line('prefix: "{}",'.format(regbank.prefix))
+
+
+def gen_isa(isa, fmt):
+    # type: (TargetISA, srcgen.Formatter) -> None
+    """
+    Generate register tables for isa.
+    """
+    if not isa.regbanks:
+        print('cargo:warning={} has no register banks'.format(isa.name))
+    with fmt.indented('pub static INFO: RegInfo = RegInfo {', '};'):
+        # Bank descriptors.
+        with fmt.indented('banks: &[', '],'):
+            for regbank in isa.regbanks:
+                gen_regbank(regbank, fmt)
+
+
+def generate(isas, out_dir):
+    # type: (Sequence[TargetISA], str) -> None
+    for isa in isas:
+        fmt = srcgen.Formatter()
+        gen_isa(isa, fmt)
+        fmt.update_file('registers-{}.rs'.format(isa.name), out_dir)

lib/cretonne/meta/isa/arm32/__init__.py

@@ -8,6 +8,7 @@ This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/arm64/__init__.py

@@ -7,6 +7,7 @@ ARMv8 CPUs running the Aarch64 architecture.
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/intel/__init__.py

@@ -17,6 +17,7 @@ is no x87 floating point support.
 
 from __future__ import absolute_import
 from . import defs
+from . import registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()

lib/cretonne/meta/isa/riscv/__init__.py

@@ -26,7 +26,7 @@ RV32G / RV64G
 """
 from __future__ import absolute_import
 from . import defs
-from . import encodings, settings # noqa
+from . import encodings, settings, registers  # noqa
 
 # Re-export the primary target ISA definition.
 ISA = defs.ISA.finish()