1f6dd0dab7
Use the information in the ISA's registers.py files to generate a RegInfo Rust data structure.
15 lines
355 B
Python
15 lines
355 B
Python
"""
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ARM 32-bit Architecture
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----------------------
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This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
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(AArch32). We support both ARM and Thumb2 instruction encodings.
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"""
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from __future__ import absolute_import
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from . import defs
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from . import registers # noqa
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# Re-export the primary target ISA definition.
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ISA = defs.ISA.finish()
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