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Update lots of isa/*/*.clif tests to precise-output (#3677)

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* Update lots of `isa/*/*.clif` tests to `precise-output`

This commit goes through the `aarch64` and `x64` subdirectories and
subjectively changes tests from `test compile` to add `precise-output`.
This then auto-updates all the test expectations so they can be
automatically instead of manually updated in the future. Not all tests
were migrated, largely subject to the whims of myself, mainly looking to
see if the test was looking for specific instructions or just checking
the whole assembly output.

* Filter out `;;` comments from test expctations

Looks like the cranelift parser picks up all comments, not just those
trailing the function, so use a convention where `;;` is used for
human-readable-comments in test cases and `;`-prefixed comments are the
test expectation.
This commit is contained in:
Alex Crichton
2022-01-10 13:38:23 -06:00
committed by GitHub
parent a8ea0ec097
commit 1ef0abb12c
58 changed files with 6883 additions and 3386 deletions
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112
cranelift/filetests/filetests/isa/x64/b1.clif
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@@ -1,72 +1,102 @@
test compile
test compile precise-output
target x86_64
function %f0(b1, i32, i32) -> i32 {
; check: pushq %rbp
; nextln: movq %rsp, %rbp
block0(v0: b1, v1: i32, v2: i32):
v3 = select.i32 v0, v1, v2
; nextln: testb $$1, %dil
; nextln: cmovnzl %esi, %edx
return v3
; nextln: movq %rdx, %rax
; nextln: movq %rbp, %rsp
; nextln: popq %rbp
; nextln: ret
}
function %f1(b1) -> i32 {
; check: pushq %rbp
; nextln: movq %rsp, %rbp
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 8)
; Inst 0: pushq %rbp
; Inst 1: movq %rsp, %rbp
; Inst 2: testb $1, %dil
; Inst 3: cmovnzl %esi, %edx
; Inst 4: movq %rdx, %rax
; Inst 5: movq %rbp, %rsp
; Inst 6: popq %rbp
; Inst 7: ret
; }}
function %f1(b1) -> i32 {
block0(v0: b1):
brnz v0, block1
jump block2
; nextln: testb $$1, %dil
; nextln: jnz label1; j label2
block1:
v1 = iconst.i32 1
return v1
; check: movl $$1, %eax
; nextln: movq %rbp, %rsp
; nextln: popq %rbp
; nextln: ret
block2:
v2 = iconst.i32 2
return v2
; check: movl $$2, %eax
; nextln: movq %rbp, %rsp
; nextln: popq %rbp
; nextln: ret
}
function %f2(b1) -> i32 {
; check: pushq %rbp
; nextln: movq %rsp, %rbp
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (successor: Block 1)
; (successor: Block 2)
; (instruction range: 0 .. 4)
; Inst 0: pushq %rbp
; Inst 1: movq %rsp, %rbp
; Inst 2: testb $1, %dil
; Inst 3: jnz label1; j label2
; Block 1:
; (original IR block: block1)
; (instruction range: 4 .. 8)
; Inst 4: movl $1, %eax
; Inst 5: movq %rbp, %rsp
; Inst 6: popq %rbp
; Inst 7: ret
; Block 2:
; (original IR block: block2)
; (instruction range: 8 .. 12)
; Inst 8: movl $2, %eax
; Inst 9: movq %rbp, %rsp
; Inst 10: popq %rbp
; Inst 11: ret
; }}
function %f2(b1) -> i32 {
block0(v0: b1):
brz v0, block1
jump block2
; nextln: testb $$1, %dil
; nextln: jz label1; j label2
block1:
v1 = iconst.i32 1
return v1
; check: movl $$1, %eax
; nextln: movq %rbp, %rsp
; nextln: popq %rbp
; nextln: ret
block2:
v2 = iconst.i32 2
return v2
; check: movl $$2, %eax
; nextln: movq %rbp, %rsp
; nextln: popq %rbp
; nextln: ret
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (successor: Block 1)
; (successor: Block 2)
; (instruction range: 0 .. 4)
; Inst 0: pushq %rbp
; Inst 1: movq %rsp, %rbp
; Inst 2: testb $1, %dil
; Inst 3: jz label1; j label2
; Block 1:
; (original IR block: block1)
; (instruction range: 4 .. 8)
; Inst 4: movl $1, %eax
; Inst 5: movq %rbp, %rsp
; Inst 6: popq %rbp
; Inst 7: ret
; Block 2:
; (original IR block: block2)
; (instruction range: 8 .. 12)
; Inst 8: movl $2, %eax
; Inst 9: movq %rbp, %rsp
; Inst 10: popq %rbp
; Inst 11: ret
; }}