1ef0abb12c
* Update lots of `isa/*/*.clif` tests to `precise-output` This commit goes through the `aarch64` and `x64` subdirectories and subjectively changes tests from `test compile` to add `precise-output`. This then auto-updates all the test expectations so they can be automatically instead of manually updated in the future. Not all tests were migrated, largely subject to the whims of myself, mainly looking to see if the test was looking for specific instructions or just checking the whole assembly output. * Filter out `;;` comments from test expctations Looks like the cranelift parser picks up all comments, not just those trailing the function, so use a convention where `;;` is used for human-readable-comments in test cases and `;`-prefixed comments are the test expectation.
103 lines
2.2 KiB
Plaintext
103 lines
2.2 KiB
Plaintext
test compile precise-output
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target x86_64
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function %f0(b1, i32, i32) -> i32 {
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block0(v0: b1, v1: i32, v2: i32):
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v3 = select.i32 v0, v1, v2
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return v3
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 8)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: testb $1, %dil
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; Inst 3: cmovnzl %esi, %edx
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; Inst 4: movq %rdx, %rax
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; Inst 5: movq %rbp, %rsp
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; Inst 6: popq %rbp
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; Inst 7: ret
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; }}
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function %f1(b1) -> i32 {
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block0(v0: b1):
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brnz v0, block1
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jump block2
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block1:
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v1 = iconst.i32 1
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return v1
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block2:
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v2 = iconst.i32 2
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (successor: Block 1)
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; (successor: Block 2)
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; (instruction range: 0 .. 4)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: testb $1, %dil
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; Inst 3: jnz label1; j label2
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; Block 1:
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; (original IR block: block1)
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; (instruction range: 4 .. 8)
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; Inst 4: movl $1, %eax
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; Inst 5: movq %rbp, %rsp
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; Inst 6: popq %rbp
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; Inst 7: ret
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; Block 2:
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; (original IR block: block2)
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; (instruction range: 8 .. 12)
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; Inst 8: movl $2, %eax
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; Inst 9: movq %rbp, %rsp
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; Inst 10: popq %rbp
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; Inst 11: ret
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; }}
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function %f2(b1) -> i32 {
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block0(v0: b1):
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brz v0, block1
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jump block2
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block1:
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v1 = iconst.i32 1
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return v1
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block2:
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v2 = iconst.i32 2
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return v2
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (successor: Block 1)
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; (successor: Block 2)
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; (instruction range: 0 .. 4)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: testb $1, %dil
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; Inst 3: jz label1; j label2
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; Block 1:
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; (original IR block: block1)
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; (instruction range: 4 .. 8)
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; Inst 4: movl $1, %eax
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; Inst 5: movq %rbp, %rsp
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; Inst 6: popq %rbp
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; Inst 7: ret
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; Block 2:
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; (original IR block: block2)
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; (instruction range: 8 .. 12)
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; Inst 8: movl $2, %eax
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; Inst 9: movq %rbp, %rsp
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; Inst 10: popq %rbp
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; Inst 11: ret
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; }}
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