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Cranelift: ensure ISA level needed for SIMD is present when SIMD is enabled. (#3816)

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Addresses #3809: when we are asked to create a Cranelift backend with
shared flags that indicate support for SIMD, we should check that the
ISA level needed for our SIMD lowerings is present.
This commit is contained in:
Chris Fallin
2022-02-16 17:29:30 -08:00
committed by GitHub
parent ef17a36852
commit 1c014d129a
55 changed files with 172 additions and 84 deletions
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2
cranelift/filetests/filetests/isa/x64/simd-lane-access-compile.clif
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@@ -1,6 +1,6 @@
test compile precise-output
set enable_simd
target x86_64 has_ssse3 has_sse41
target x86_64 has_sse3 has_ssse3 has_sse41
;; shuffle

2
cranelift/filetests/filetests/runtests/simd-bitselect.clif
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@@ -1,7 +1,7 @@
test run
set enable_simd
target aarch64
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %bitselect_i32x4(i32x4, i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4, v2: i32x4):

2
cranelift/filetests/filetests/runtests/simd-comparison.clif
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@@ -2,7 +2,7 @@ test run
target aarch64
; target s390x TODO: Not yet implemented on s390x
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %icmp_eq_i8x16() -> b8 {
block0:

2
cranelift/filetests/filetests/runtests/simd-conversion.clif
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@@ -2,7 +2,7 @@ test run
target aarch64
; target s390x TODO: Not yet implemented on s390x
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %fcvt_from_sint(i32x4) -> f32x4 {
block0(v0: i32x4):

2
cranelift/filetests/filetests/runtests/simd-extractlane.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %extractlane_4(i8x16) -> i8 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-iabs.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %iabs_i8x16(i8x16) -> i8x16 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-insertlane.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %insertlane_15(i8x16, i8) -> i8x16 {
block0(v0: i8x16, v1: i8):

2
cranelift/filetests/filetests/runtests/simd-lane-access.clif
View File

@@ -2,7 +2,7 @@ test run
target aarch64
; target s390x TODO: Not yet implemented on s390x
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
;; shuffle

2
cranelift/filetests/filetests/runtests/simd-logical.clif
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@@ -2,7 +2,7 @@ test run
target aarch64
; target s390x TODO: Not yet implemented on s390x
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %bnot() -> b32 {
block0:

2
cranelift/filetests/filetests/runtests/simd-saddsat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %saddsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-shuffle.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %shuffle_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-snarrow.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %snarrow_i16x8(i16x8, i16x8) -> i8x16 {
block0(v0: i16x8, v1: i16x8):

2
cranelift/filetests/filetests/runtests/simd-splat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %splat_i8x16(i8) -> i8x16 {
block0(v0: i8):

2
cranelift/filetests/filetests/runtests/simd-sqmulroundsat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %sqmulrs_i16x8(i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8):

2
cranelift/filetests/filetests/runtests/simd-ssubsat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %ssubsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-swidenhigh.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %swidenhigh_i8x16(i8x16) -> i16x8 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-swidenlow.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %swidenlow_i8x16(i8x16) -> i16x8 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-swizzle.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %swizzle_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-uaddsat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %uaddsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-unarrow.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %unarrow_i16x8(i16x8, i16x8) -> i8x16 {
block0(v0: i16x8, v1: i16x8):

2
cranelift/filetests/filetests/runtests/simd-usubsat.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %usubsat_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):

2
cranelift/filetests/filetests/runtests/simd-uwidenhigh.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %uwidenhigh_i8x16(i8x16) -> i16x8 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-uwidenlow.clif
View File

@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %uwidenlow_i8x16(i8x16) -> i16x8 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-vconst.clif
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@@ -2,7 +2,7 @@ test run
; target s390x TODO: Not yet implemented on s390x
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %vconst_zeroes() -> b1 {

2
cranelift/filetests/filetests/runtests/simd-vhighbits.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %vhighbits_i8x16(i8x16) -> i16 {
block0(v0: i8x16):

2
cranelift/filetests/filetests/runtests/simd-vselect.clif
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@@ -3,7 +3,7 @@ test run
; target s390x TODO: Not yet implemented on s390x
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %vselect_i8x16() -> i8x16 {
block0:

2
cranelift/filetests/filetests/runtests/simd-wideningpairwisedotproducts.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %wpdps(i16x8, i16x8) -> i32x4 {
block0(v0: i16x8, v1: i16x8):

2
cranelift/filetests/filetests/runtests/smulhi.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %smulhi_i16(i16, i16) -> i16 {
block0(v0: i16, v1: i16):

2
cranelift/filetests/filetests/runtests/umulhi.clif
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@@ -2,7 +2,7 @@ test interpret
test run
target aarch64
set enable_simd
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
target s390x
function %umulhi_i16(i16, i16) -> i16 {

2
cranelift/filetests/filetests/verifier/scalar-to-vector.clif
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@@ -1,7 +1,7 @@
test verifier
set enable_simd=true
target aarch64
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %scalar_to_vector() {
block0:

2
cranelift/filetests/filetests/verifier/simd-lane-index.clif
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@@ -1,7 +1,7 @@
test verifier
set enable_simd
target aarch64
target x86_64
target x86_64 has_sse3 has_ssse3 has_sse41
function %insertlane_i32x4() {
block0:

17
cranelift/filetests/src/function_runner.rs
View File

@@ -1,4 +1,5 @@
//! Provides functionality for compiling and running CLIF IR for `run` tests.
use anyhow::Result;
use core::mem;
use cranelift_codegen::data_value::DataValue;
use cranelift_codegen::ir::{condcodes::IntCC, Function, InstBuilder, Signature};
@@ -27,7 +28,7 @@ use thiserror::Error;
///
/// let code = "test run \n function %add(i32, i32) -> i32 { block0(v0:i32, v1:i32): v2 = iadd v0, v1 return v2 }".into();
/// let func = parse_functions(code).unwrap().into_iter().nth(0).unwrap();
/// let mut compiler = SingleFunctionCompiler::with_default_host_isa();
/// let mut compiler = SingleFunctionCompiler::with_default_host_isa().unwrap();
/// let compiled_func = compiler.compile(func).unwrap();
/// println!("Address of compiled function: {:p}", compiled_func.as_ptr());
/// ```
@@ -46,16 +47,16 @@ impl SingleFunctionCompiler {
}
/// Build a [SingleFunctionCompiler] using the host machine's ISA and the passed flags.
pub fn with_host_isa(flags: settings::Flags) -> Self {
pub fn with_host_isa(flags: settings::Flags) -> Result<Self> {
let builder =
builder_with_options(true).expect("Unable to build a TargetIsa for the current host");
let isa = builder.finish(flags);
Self::new(isa)
let isa = builder.finish(flags)?;
Ok(Self::new(isa))
}
/// Build a [SingleFunctionCompiler] using the host machine's ISA and the default flags for this
/// ISA.
pub fn with_default_host_isa() -> Self {
pub fn with_default_host_isa() -> Result<Self> {
let flags = settings::Flags::new(settings::builder());
Self::with_host_isa(flags)
}
@@ -135,7 +136,7 @@ impl Trampoline {
///
/// let code = "test run \n function %add(i32, i32) -> i32 { block0(v0:i32, v1:i32): v2 = iadd v0, v1 return v2 }".into();
/// let func = parse_functions(code).unwrap().into_iter().nth(0).unwrap();
/// let mut compiler = SingleFunctionCompiler::with_default_host_isa();
/// let mut compiler = SingleFunctionCompiler::with_default_host_isa().unwrap();
/// let compiled_func = compiler.compile(func).unwrap();
///
/// let returned = compiled_func.call(&vec![DataValue::I32(2), DataValue::I32(40)]);
@@ -377,7 +378,7 @@ mod test {
let function = test_file.functions[0].0.clone();
// execute function
let mut compiler = SingleFunctionCompiler::with_default_host_isa();
let mut compiler = SingleFunctionCompiler::with_default_host_isa().unwrap();
let compiled_function = compiler.compile(function).unwrap();
let returned = compiled_function.call(&[]);
assert_eq!(returned, vec![DataValue::B(true)])
@@ -395,7 +396,7 @@ mod test {
}",
);
let compiler = SingleFunctionCompiler::with_default_host_isa();
let compiler = SingleFunctionCompiler::with_default_host_isa().unwrap();
let trampoline = make_trampoline(&function.signature, compiler.isa.as_ref());
assert!(format!("{}", trampoline).ends_with(
"sig0 = (f32, i8, i64x2, b1) -> f32x4, b64 fast

2
cranelift/filetests/src/test_run.rs
View File

@@ -51,7 +51,7 @@ impl SubTest for TestRun {
let test_env = RuntestEnvironment::parse(&context.details.comments[..])?;
let mut compiler = SingleFunctionCompiler::with_host_isa(context.flags.clone());
let mut compiler = SingleFunctionCompiler::with_host_isa(context.flags.clone())?;
for comment in context.details.comments.iter() {
if let Some(command) = parse_run_command(comment.text, &func.signature)? {
trace!("Parsed run command: {}", command);