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Add Intel encodings for the bint instructions.

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Convert b1 to i32 or i64 by zero-extending the byte.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-19 12:01:28 -07:00
parent 421a88123d
commit 1a662575a5
4 changed files with 40 additions and 0 deletions
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7
cranelift/filetests/isa/intel/binary32.cton
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@@ -326,6 +326,13 @@ ebb0:
; asm: setbe %dl ; asm: setbe %dl
[-,%rdx] v319 = icmp ule v2, v1 ; bin: 39 ce 0f 96 c2 [-,%rdx] v319 = icmp ule v2, v1 ; bin: 39 ce 0f 96 c2
; Bool-to-int conversions.
; asm: movzbl %bl, %ecx
[-,%rcx] v350 = bint.i32 v300 ; bin: 0f b6 cb
; asm: movzbl %dl, %esi
[-,%rsi] v351 = bint.i32 v301 ; bin: 0f b6 f2
; asm: call foo ; asm: call foo
call fn0() ; bin: e8 PCRel4(fn0) 00000000 call fn0() ; bin: e8 PCRel4(fn0) 00000000

14
cranelift/filetests/isa/intel/binary64.cton
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@@ -264,6 +264,13 @@ ebb0:
; asm: setbe %dl ; asm: setbe %dl
[-,%rdx] v319 = icmp ule v2, v3 ; bin: 4c 39 d6 0f 96 c2 [-,%rdx] v319 = icmp ule v2, v3 ; bin: 4c 39 d6 0f 96 c2
; Bool-to-int conversions.
; asm: movzbq %bl, %rcx
[-,%rcx] v350 = bint.i64 v300 ; bin: 48 0f b6 cb
; asm: movzbq %dl, %rsi
[-,%rsi] v351 = bint.i64 v301 ; bin: 48 0f b6 f2
; asm: testq %rcx, %rcx ; asm: testq %rcx, %rcx
; asm: je ebb1 ; asm: je ebb1
brz v1, ebb1 ; bin: 48 85 c9 74 1b brz v1, ebb1 ; bin: 48 85 c9 74 1b
@@ -556,6 +563,13 @@ ebb0:
; asm: setbe %dl ; asm: setbe %dl
[-,%rdx] v319 = icmp ule v2, v3 ; bin: 44 39 d6 0f 96 c2 [-,%rdx] v319 = icmp ule v2, v3 ; bin: 44 39 d6 0f 96 c2
; Bool-to-int conversions.
; asm: movzbl %bl, %ecx
[-,%rcx] v350 = bint.i32 v300 ; bin: 40 0f b6 cb
; asm: movzbl %dl, %esi
[-,%rsi] v351 = bint.i32 v301 ; bin: 40 0f b6 f2
; asm: testl %ecx, %ecx ; asm: testl %ecx, %ecx
; asm: je ebb1x ; asm: je ebb1x
brz v1, ebb1 ; bin: 40 85 c9 74 1b brz v1, ebb1 ; bin: 40 85 c9 74 1b

11
lib/cretonne/meta/isa/intel/encodings.py
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@@ -182,3 +182,14 @@ I32.enc(base.icmp.i32, *r.icscc(0x39))
I64.enc(base.icmp.i64, *r.icscc.rex(0x39, w=1)) I64.enc(base.icmp.i64, *r.icscc.rex(0x39, w=1))
I64.enc(base.icmp.i32, *r.icscc.rex(0x39)) I64.enc(base.icmp.i32, *r.icscc.rex(0x39))
I64.enc(base.icmp.i32, *r.icscc(0x39)) I64.enc(base.icmp.i32, *r.icscc(0x39))
#
# Convert bool to int.
#
# This assumes that b1 is represented as an 8-bit low register with the value 0
# or 1.
I32.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
I64.enc(base.bint.i64.b1, *r.urm.rex(0x0f, 0xb6, w=1))
I64.enc(base.bint.i64.b1, *r.urm_abcd(0x0f, 0xb6)) # zext to i64 implicit.
I64.enc(base.bint.i32.b1, *r.urm.rex(0x0f, 0xb6))
I64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))

8
lib/cretonne/meta/isa/intel/recipes.py
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@@ -224,6 +224,14 @@ urm = TailRecipe(
modrm_rr(in_reg0, out_reg0, sink); modrm_rr(in_reg0, out_reg0, sink);
''') ''')
# XX /r. Same as urm, but input limited to ABCD.
urm_abcd = TailRecipe(
'urm_abcd', Unary, size=1, ins=ABCD, outs=GPR,
emit='''
PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
modrm_rr(in_reg0, out_reg0, sink);
''')
# XX /r, for regmove instructions. # XX /r, for regmove instructions.
rmov = TailRecipe( rmov = TailRecipe(
'ur', RegMove, size=1, ins=GPR, outs=(), 'ur', RegMove, size=1, ins=GPR, outs=(),