From 1a662575a58a4efe809c9c174d01e53fb2bb8f43 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Wed, 19 Jul 2017 12:01:28 -0700
Subject: [PATCH] Add Intel encodings for the bint instructions.

Convert b1 to i32 or i64 by zero-extending the byte.
---
 cranelift/filetests/isa/intel/binary32.cton |  7 +++++++
 cranelift/filetests/isa/intel/binary64.cton | 14 ++++++++++++++
 lib/cretonne/meta/isa/intel/encodings.py    | 11 +++++++++++
 lib/cretonne/meta/isa/intel/recipes.py      |  8 ++++++++
 4 files changed, 40 insertions(+)

diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton
index 2ee9396bf0..7e95f84818 100644
--- a/cranelift/filetests/isa/intel/binary32.cton
+++ b/cranelift/filetests/isa/intel/binary32.cton
@@ -326,6 +326,13 @@ ebb0:
     ; asm: setbe %dl
     [-,%rdx]            v319 = icmp ule v2, v1  ; bin: 39 ce 0f 96 c2
 
+    ; Bool-to-int conversions.
+
+    ; asm: movzbl %bl, %ecx
+    [-,%rcx]             v350 = bint.i32 v300   ; bin: 0f b6 cb
+    ; asm: movzbl %dl, %esi
+    [-,%rsi]             v351 = bint.i32 v301   ; bin: 0f b6 f2
+
     ; asm: call foo
     call fn0()                                  ; bin: e8 PCRel4(fn0) 00000000
 
diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton
index 00524afc4e..6222a1e7be 100644
--- a/cranelift/filetests/isa/intel/binary64.cton
+++ b/cranelift/filetests/isa/intel/binary64.cton
@@ -264,6 +264,13 @@ ebb0:
     ; asm: setbe %dl
     [-,%rdx]            v319 = icmp ule v2, v3  ; bin: 4c 39 d6 0f 96 c2
 
+    ; Bool-to-int conversions.
+
+    ; asm: movzbq %bl, %rcx
+    [-,%rcx]             v350 = bint.i64 v300   ; bin: 48 0f b6 cb
+    ; asm: movzbq %dl, %rsi
+    [-,%rsi]             v351 = bint.i64 v301   ; bin: 48 0f b6 f2
+
     ; asm: testq %rcx, %rcx
     ; asm: je ebb1
     brz v1, ebb1                                ; bin: 48 85 c9 74 1b
@@ -556,6 +563,13 @@ ebb0:
     ; asm: setbe %dl
     [-,%rdx]            v319 = icmp ule v2, v3  ; bin: 44 39 d6 0f 96 c2
 
+    ; Bool-to-int conversions.
+
+    ; asm: movzbl %bl, %ecx
+    [-,%rcx]             v350 = bint.i32 v300   ; bin: 40 0f b6 cb
+    ; asm: movzbl %dl, %esi
+    [-,%rsi]             v351 = bint.i32 v301   ; bin: 40 0f b6 f2
+
     ; asm: testl %ecx, %ecx
     ; asm: je ebb1x
     brz v1, ebb1                                ; bin: 40 85 c9 74 1b
diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py
index 9af8d6484d..6b04ae110d 100644
--- a/lib/cretonne/meta/isa/intel/encodings.py
+++ b/lib/cretonne/meta/isa/intel/encodings.py
@@ -182,3 +182,14 @@ I32.enc(base.icmp.i32, *r.icscc(0x39))
 I64.enc(base.icmp.i64, *r.icscc.rex(0x39, w=1))
 I64.enc(base.icmp.i32, *r.icscc.rex(0x39))
 I64.enc(base.icmp.i32, *r.icscc(0x39))
+
+#
+# Convert bool to int.
+#
+# This assumes that b1 is represented as an 8-bit low register with the value 0
+# or 1.
+I32.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
+I64.enc(base.bint.i64.b1, *r.urm.rex(0x0f, 0xb6, w=1))
+I64.enc(base.bint.i64.b1, *r.urm_abcd(0x0f, 0xb6))  # zext to i64 implicit.
+I64.enc(base.bint.i32.b1, *r.urm.rex(0x0f, 0xb6))
+I64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py
index 7fa7ca1bf3..8ae65f4723 100644
--- a/lib/cretonne/meta/isa/intel/recipes.py
+++ b/lib/cretonne/meta/isa/intel/recipes.py
@@ -224,6 +224,14 @@ urm = TailRecipe(
         modrm_rr(in_reg0, out_reg0, sink);
         ''')
 
+# XX /r. Same as urm, but input limited to ABCD.
+urm_abcd = TailRecipe(
+        'urm_abcd', Unary, size=1, ins=ABCD, outs=GPR,
+        emit='''
+        PUT_OP(bits, rex2(in_reg0, out_reg0), sink);
+        modrm_rr(in_reg0, out_reg0, sink);
+        ''')
+
 # XX /r, for regmove instructions.
 rmov = TailRecipe(
         'ur', RegMove, size=1, ins=GPR, outs=(),