Rename meta/target -> meta/isa.

Clarify terminology by always referring to a 'Target ISA' instead of just
'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python
code.

This is only to clarify terminology and not at all because Cargo insists on
using the 'target' sub-directory for build products. Oh, no. Not at all.

cranelift/docs/metaref.rst

@@ -299,17 +299,17 @@ Targets
 =======
 
 Cretonne can be compiled with support for multiple target instruction set
-architectures. Each ISA is represented by a :py:class:`cretonne.Target` instance.
+architectures. Each ISA is represented by a :py:class:`cretonne.TargetISA` instance.
 
-.. autoclass:: Target
+.. autoclass:: TargetISA
 
 The definitions for each supported target live in a package under
-:file:`meta/target`.
+:file:`meta/isa`.
 
-.. automodule:: target
+.. automodule:: isa
     :members:
 
-.. automodule:: target.riscv
+.. automodule:: isa.riscv
 
 
 Glossary

meta/build.py

@@ -3,7 +3,7 @@
 # This script is run from src/libcretonne/build.rs to generate Rust files.
 
 import argparse
-import target
+import isa
 import gen_instr
 import gen_build_deps
 
@@ -13,7 +13,7 @@ parser.add_argument('--out-dir', help='set output directory')
 args = parser.parse_args()
 out_dir = args.out_dir
 
-targets = target.all_targets()
+isas = isa.all_isas()
 
-gen_instr.generate(targets, out_dir)
+gen_instr.generate(isas, out_dir)
 gen_build_deps.generate()

meta/cretonne/__init__.py

@@ -717,14 +717,14 @@ class BoundInstruction(object):
         return (self.inst, self.typevars)
 
 
-# Defining targets
+# Defining target ISAs.
 
 
-class Target(object):
+class TargetISA(object):
     """
     A target instruction set architecture.
 
-    The `Target` class collects everything known about a target ISA.
+    The `TargetISA` class collects everything known about a target ISA.
 
     :param name: Short mnemonic name for the ISA.
     :param instruction_groups: List of `InstructionGroup` instances that are
@@ -741,15 +741,15 @@ class CPUMode(object):
     A CPU mode determines which instruction encodings are active.
 
     All instruction encodings are associated with exactly one `CPUMode`, and
-    all CPU modes are associated with exactly one `Target`.
+    all CPU modes are associated with exactly one `TargetISA`.
 
     :param name: Short mnemonic name for the CPU mode.
-    :param target: Associated `Target`.
+    :param target: Associated `TargetISA`.
     """
 
-    def __init__(self, name, target):
+    def __init__(self, name, isa):
         self.name = name
-        self.target = target
+        self.isa = isa
         self.encodings = []
 
     def enc(self, *args, **kwargs):

meta/gen_instr.py

@@ -161,11 +161,11 @@ def gen_instruction_data_impl(fmt):
                                     .format(i))
 
 
-def collect_instr_groups(targets):
+def collect_instr_groups(isas):
     seen = set()
     groups = []
-    for t in targets:
-        for g in t.instruction_groups:
+    for isa in isas:
+        for g in isa.instruction_groups:
             if g not in seen:
                 groups.append(g)
                 seen.add(g)
@@ -181,7 +181,7 @@ def gen_opcodes(groups, fmt):
 
     fmt.doc_comment('An instruction opcode.')
     fmt.doc_comment('')
-    fmt.doc_comment('All instructions from all supported targets are present.')
+    fmt.doc_comment('All instructions from all supported ISAs are present.')
     fmt.line('#[derive(Copy, Clone, PartialEq, Eq, Debug)]')
     instrs = []
     with fmt.indented('pub enum Opcode {', '}'):
@@ -360,8 +360,8 @@ def gen_type_constraints(fmt, instrs):
             fmt.line('OperandConstraint::{},'.format(c))
 
 
-def generate(targets, out_dir):
-    groups = collect_instr_groups(targets)
+def generate(isas, out_dir):
+    groups = collect_instr_groups(isas)
 
     # opcodes.rs
     fmt = srcgen.Formatter()

meta/isa/__init__.py

@@ -0,0 +1,17 @@
+"""
+Cretonne target ISA definitions
+-------------------------------
+
+The :py:mod:`isa` package contains sub-packages for each target instruction set
+architecture supported by Cretonne.
+"""
+
+from . import riscv
+
+
+def all_isas():
+    """
+    Get a list of all the supported target ISAs. Each target ISA is represented
+    as a :py:class:`cretonne.TargetISA` instance.
+    """
+    return [riscv.isa]

meta/isa/riscv/__init__.py

@@ -28,6 +28,6 @@ RV32G / RV64G
 import defs
 import encodings
 
-# Re-export the primary target definition.
-target = defs.target
+# Re-export the primary target ISA definition.
+isa = defs.isa
 

meta/isa/riscv/defs.py

@@ -0,0 +1,14 @@
+"""
+RISC-V definitions.
+
+Commonly used definitions.
+"""
+
+from cretonne import TargetISA, CPUMode
+import cretonne.base
+
+isa = TargetISA('riscv', [cretonne.base.instructions])
+
+# CPU modes for 32-bit and 64-bit operation.
+RV32 = CPUMode('RV32', isa)
+RV64 = CPUMode('RV64', isa)

meta/target/__init__.py

@@ -1,17 +0,0 @@
-"""
-Cretonne target definitions
----------------------------
-
-The :py:mod:`target` package contains sub-packages for each target instruction
-set architecture supported by Cretonne.
-"""
-
-from . import riscv
-
-
-def all_targets():
-    """
-    Get a list of all the supported targets. Each target is represented as a
-    :py:class:`cretonne.Target` instance.
-    """
-    return [riscv.target]

meta/target/riscv/defs.py

@@ -1,14 +0,0 @@
-"""
-RISC-V definitions.
-
-Commonly used definitions.
-"""
-
-from cretonne import Target, CPUMode
-import cretonne.base
-
-target = Target('riscv', [cretonne.base.instructions])
-
-# CPU modes for 32-bit and 64-bit operation.
-RV32 = CPUMode('RV32', target)
-RV64 = CPUMode('RV64', target)