1a4d07d437
Clarify terminology by always referring to a 'Target ISA' instead of just 'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python code. This is only to clarify terminology and not at all because Cargo insists on using the 'target' sub-directory for build products. Oh, no. Not at all.
30 lines
953 B
Python
30 lines
953 B
Python
"""
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RISC-V Encodings.
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"""
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from cretonne import base
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from cretonne.types import i32, i64
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from defs import RV32, RV64
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from recipes import OP, R
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# Basic arithmetic binary instructions are encoded in an R-type instruction.
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for inst, f3, f7 in [
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(base.iadd, 0b000, 0b0000000),
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(base.isub, 0b000, 0b0100000),
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(base.bxor, 0b100, 0b0000000),
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(base.bor, 0b110, 0b0000000),
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(base.band, 0b111, 0b0000000)
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]:
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RV32.enc(inst.i32, R, OP(f3, f7))
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RV64.enc(inst.i64, R, OP(f3, f7))
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# Dynamic shifts have the same masking semantics as the cton base instructions
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for inst, f3, f7 in [
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(base.ishl, 0b001, 0b0000000),
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(base.ushr, 0b101, 0b0000000),
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(base.sshr, 0b101, 0b0100000),
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]:
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RV32.enc(inst.i32.i32, R, OP(f3, f7))
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RV64.enc(inst.i64.i64, R, OP(f3, f7))
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# Allow i32 shift amounts in 64-bit shifts.
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RV64.enc(inst.i64.i32, R, OP(f3, f7))
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