Rename meta/target -> meta/isa.

Clarify terminology by always referring to a 'Target ISA' instead of just
'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python
code.

This is only to clarify terminology and not at all because Cargo insists on
using the 'target' sub-directory for build products. Oh, no. Not at all.

meta/isa/__init__.py

@@ -0,0 +1,17 @@
+"""
+Cretonne target ISA definitions
+-------------------------------
+
+The :py:mod:`isa` package contains sub-packages for each target instruction set
+architecture supported by Cretonne.
+"""
+
+from . import riscv
+
+
+def all_isas():
+    """
+    Get a list of all the supported target ISAs. Each target ISA is represented
+    as a :py:class:`cretonne.TargetISA` instance.
+    """
+    return [riscv.isa]

meta/isa/riscv/__init__.py

@@ -0,0 +1,33 @@
+"""
+RISC-V Target
+-------------
+
+`RISC-V <http://riscv.org/>`_ is an open instruction set architecture
+originally developed at UC Berkeley. It is a RISC-style ISA with either a
+32-bit (RV32I) or 64-bit (RV32I) base instruction set and a number of optional
+extensions:
+
+RV32M / RV64M
+    Integer multiplication and division.
+
+RV32A / RV64A
+    Atomics.
+
+RV32F / RV64F
+    Single-precision IEEE floating point.
+
+RV32D / RV64D
+    Double-precision IEEE floating point.
+
+RV32G / RV64G
+    General purpose instruction sets. This represents the union of the I, M, A,
+    F, and D instruction sets listed above.
+
+"""
+
+import defs
+import encodings
+
+# Re-export the primary target ISA definition.
+isa = defs.isa
+

meta/isa/riscv/defs.py

@@ -0,0 +1,14 @@
+"""
+RISC-V definitions.
+
+Commonly used definitions.
+"""
+
+from cretonne import TargetISA, CPUMode
+import cretonne.base
+
+isa = TargetISA('riscv', [cretonne.base.instructions])
+
+# CPU modes for 32-bit and 64-bit operation.
+RV32 = CPUMode('RV32', isa)
+RV64 = CPUMode('RV64', isa)

meta/isa/riscv/encodings.py

@@ -0,0 +1,29 @@
+"""
+RISC-V Encodings.
+"""
+from cretonne import base
+from cretonne.types import i32, i64
+from defs import RV32, RV64
+from recipes import OP, R
+
+# Basic arithmetic binary instructions are encoded in an R-type instruction.
+for inst,           f3,    f7 in [
+        (base.iadd, 0b000, 0b0000000),
+        (base.isub, 0b000, 0b0100000),
+        (base.bxor, 0b100, 0b0000000),
+        (base.bor,  0b110, 0b0000000),
+        (base.band, 0b111, 0b0000000)
+        ]:
+    RV32.enc(inst.i32, R, OP(f3, f7))
+    RV64.enc(inst.i64, R, OP(f3, f7))
+
+# Dynamic shifts have the same masking semantics as the cton base instructions
+for inst,           f3,    f7 in [
+        (base.ishl, 0b001, 0b0000000),
+        (base.ushr, 0b101, 0b0000000),
+        (base.sshr, 0b101, 0b0100000),
+        ]:
+    RV32.enc(inst.i32.i32, R, OP(f3, f7))
+    RV64.enc(inst.i64.i64, R, OP(f3, f7))
+    # Allow i32 shift amounts in 64-bit shifts.
+    RV64.enc(inst.i64.i32, R, OP(f3, f7))

meta/isa/riscv/recipes.py

@@ -0,0 +1,44 @@
+"""
+RISC-V Encoding recipes.
+
+The encoding recipes defined here more or less correspond to the RISC-V native
+instruction formats described in the reference:
+
+    The RISC-V Instruction Set Manual
+    Volume I: User-Level ISA
+    Version 2.1
+"""
+from cretonne import EncRecipe
+from cretonne.formats import Binary
+
+# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
+# instructions have 11 as the two low bits, with bits 6:2 determining the base
+# opcode.
+#
+# Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
+# The functions below encode the encbits.
+
+def LOAD(funct3):
+    assert funct3 <= 0b111
+    return 0b00000 | (funct3 << 5)
+
+def STORE(funct3):
+    assert funct3 <= 0b111
+    return 0b01000 | (funct3 << 5)
+
+def BRANCH(funct3):
+    assert funct3 <= 0b111
+    return 0b11000 | (funct3 << 5)
+
+def OPIMM(funct3):
+    assert funct3 <= 0b111
+    return 0b00100 | (funct3 << 5)
+
+def OP(funct3, funct7):
+    assert funct3 <= 0b111
+    assert funct7 <= 0b1111111
+    return 0b01100 | (funct3 << 5) | (funct7 << 8)
+
+# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
+# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
+R = EncRecipe('R', Binary)