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aarch64: pass a lowering context to gen_copy_reg_to_arg;

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This commit is contained in:
Benjamin Bouvier
2020-04-24 17:38:23 +02:00
parent 0b13d8c848
commit 19b5b0cc7b
3 changed files with 10 additions and 13 deletions
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14
cranelift/codegen/src/isa/aarch64/abi.rs
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@@ -331,18 +331,19 @@ fn store_stack_fp(fp_offset: i64, from_reg: Reg, ty: Type) -> Inst {
store_stack(MemArg::FPOffset(fp_offset), from_reg, ty) store_stack(MemArg::FPOffset(fp_offset), from_reg, ty)
} }
fn store_stack_sp( fn store_stack_sp<C: LowerCtx<I = Inst>>(
ctx: &mut C,
sp_offset: i64, sp_offset: i64,
from_reg: Reg, from_reg: Reg,
ty: Type, ty: Type,
tmp1: Writable<Reg>,
tmp2: Writable<Reg>,
) -> Vec<Inst> { ) -> Vec<Inst> {
if SImm9::maybe_from_i64(sp_offset).is_some() { if SImm9::maybe_from_i64(sp_offset).is_some() {
vec![store_stack(MemArg::SPOffset(sp_offset), from_reg, ty)] vec![store_stack(MemArg::SPOffset(sp_offset), from_reg, ty)]
} else { } else {
// mem_finalize will try to generate an add, but in an addition, x31 is the zero register, // mem_finalize will try to generate an add, but in an addition, x31 is the zero register,
// not sp! So we have to synthesize the full add here. // not sp! So we have to synthesize the full add here.
let tmp1 = ctx.tmp(RegClass::I64, I64);
let tmp2 = ctx.tmp(RegClass::I64, I64);
let mut result = Vec::new(); let mut result = Vec::new();
// tmp1 := sp // tmp1 := sp
result.push(Inst::Mov { result.push(Inst::Mov {
@@ -974,12 +975,11 @@ impl ABICall for AArch64ABICall {
adjust_stack(self.sig.stack_arg_space as u64, /* is_sub = */ false) adjust_stack(self.sig.stack_arg_space as u64, /* is_sub = */ false)
} }
fn gen_copy_reg_to_arg( fn gen_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
&self, &self,
ctx: &mut C,
idx: usize, idx: usize,
from_reg: Reg, from_reg: Reg,
tmp1: Writable<Reg>,
tmp2: Writable<Reg>,
) -> Vec<Inst> { ) -> Vec<Inst> {
match &self.sig.args[idx] { match &self.sig.args[idx] {
&ABIArg::Reg(reg, ty) => vec![Inst::gen_move( &ABIArg::Reg(reg, ty) => vec![Inst::gen_move(
@@ -987,7 +987,7 @@ impl ABICall for AArch64ABICall {
from_reg, from_reg,
ty, ty,
)], )],
&ABIArg::Stack(off, ty) => store_stack_sp(off, from_reg, ty, tmp1, tmp2), &ABIArg::Stack(off, ty) => store_stack_sp(ctx, off, from_reg, ty),
} }
} }

4
cranelift/codegen/src/isa/aarch64/lower.rs
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@@ -1982,11 +1982,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
ctx.emit(inst); ctx.emit(inst);
} }
assert!(inputs.len() == abi.num_args()); assert!(inputs.len() == abi.num_args());
let tmp1 = ctx.tmp(RegClass::I64, I64);
let tmp2 = ctx.tmp(RegClass::I64, I64);
for (i, input) in inputs.iter().enumerate() { for (i, input) in inputs.iter().enumerate() {
let arg_reg = input_to_reg(ctx, *input, NarrowValueMode::None); let arg_reg = input_to_reg(ctx, *input, NarrowValueMode::None);
for inst in abi.gen_copy_reg_to_arg(i, arg_reg, tmp1, tmp2) { for inst in abi.gen_copy_reg_to_arg(ctx, i, arg_reg) {
ctx.emit(inst); ctx.emit(inst);
} }
} }

5
cranelift/codegen/src/machinst/abi.rs
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@@ -133,12 +133,11 @@ pub trait ABICall {
fn num_args(&self) -> usize; fn num_args(&self) -> usize;
/// Copy an argument value from a source register, prior to the call. /// Copy an argument value from a source register, prior to the call.
fn gen_copy_reg_to_arg( fn gen_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
&self, &self,
ctx: &mut C,
idx: usize, idx: usize,
from_reg: Reg, from_reg: Reg,
tmp1: Writable<Reg>,
tmp2: Writable<Reg>,
) -> Vec<Self::I>; ) -> Vec<Self::I>;
/// Copy a return value into a destination register, after the call returns. /// Copy a return value into a destination register, after the call returns.