From 19b5b0cc7b2fe935e68f8168895d157d0077df32 Mon Sep 17 00:00:00 2001
From: Benjamin Bouvier <public@benj.me>
Date: Fri, 24 Apr 2020 17:38:23 +0200
Subject: [PATCH] aarch64: pass a lowering context to gen_copy_reg_to_arg;

---
 cranelift/codegen/src/isa/aarch64/abi.rs   | 14 +++++++-------
 cranelift/codegen/src/isa/aarch64/lower.rs |  4 +---
 cranelift/codegen/src/machinst/abi.rs      |  5 ++---
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/cranelift/codegen/src/isa/aarch64/abi.rs b/cranelift/codegen/src/isa/aarch64/abi.rs
index a8fc48d794..860089d23d 100644
--- a/cranelift/codegen/src/isa/aarch64/abi.rs
+++ b/cranelift/codegen/src/isa/aarch64/abi.rs
@@ -331,18 +331,19 @@ fn store_stack_fp(fp_offset: i64, from_reg: Reg, ty: Type) -> Inst {
     store_stack(MemArg::FPOffset(fp_offset), from_reg, ty)
 }
 
-fn store_stack_sp(
+fn store_stack_sp<C: LowerCtx<I = Inst>>(
+    ctx: &mut C,
     sp_offset: i64,
     from_reg: Reg,
     ty: Type,
-    tmp1: Writable<Reg>,
-    tmp2: Writable<Reg>,
 ) -> Vec<Inst> {
     if SImm9::maybe_from_i64(sp_offset).is_some() {
         vec![store_stack(MemArg::SPOffset(sp_offset), from_reg, ty)]
     } else {
         // mem_finalize will try to generate an add, but in an addition, x31 is the zero register,
         // not sp! So we have to synthesize the full add here.
+        let tmp1 = ctx.tmp(RegClass::I64, I64);
+        let tmp2 = ctx.tmp(RegClass::I64, I64);
         let mut result = Vec::new();
         // tmp1 := sp
         result.push(Inst::Mov {
@@ -974,12 +975,11 @@ impl ABICall for AArch64ABICall {
         adjust_stack(self.sig.stack_arg_space as u64, /* is_sub = */ false)
     }
 
-    fn gen_copy_reg_to_arg(
+    fn gen_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
         &self,
+        ctx: &mut C,
         idx: usize,
         from_reg: Reg,
-        tmp1: Writable<Reg>,
-        tmp2: Writable<Reg>,
     ) -> Vec<Inst> {
         match &self.sig.args[idx] {
             &ABIArg::Reg(reg, ty) => vec![Inst::gen_move(
@@ -987,7 +987,7 @@ impl ABICall for AArch64ABICall {
                 from_reg,
                 ty,
             )],
-            &ABIArg::Stack(off, ty) => store_stack_sp(off, from_reg, ty, tmp1, tmp2),
+            &ABIArg::Stack(off, ty) => store_stack_sp(ctx, off, from_reg, ty),
         }
     }
 
diff --git a/cranelift/codegen/src/isa/aarch64/lower.rs b/cranelift/codegen/src/isa/aarch64/lower.rs
index 66e708249d..505a742607 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.rs
+++ b/cranelift/codegen/src/isa/aarch64/lower.rs
@@ -1982,11 +1982,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
                 ctx.emit(inst);
             }
             assert!(inputs.len() == abi.num_args());
-            let tmp1 = ctx.tmp(RegClass::I64, I64);
-            let tmp2 = ctx.tmp(RegClass::I64, I64);
             for (i, input) in inputs.iter().enumerate() {
                 let arg_reg = input_to_reg(ctx, *input, NarrowValueMode::None);
-                for inst in abi.gen_copy_reg_to_arg(i, arg_reg, tmp1, tmp2) {
+                for inst in abi.gen_copy_reg_to_arg(ctx, i, arg_reg) {
                     ctx.emit(inst);
                 }
             }
diff --git a/cranelift/codegen/src/machinst/abi.rs b/cranelift/codegen/src/machinst/abi.rs
index b5bbbb9cb5..48278c537a 100644
--- a/cranelift/codegen/src/machinst/abi.rs
+++ b/cranelift/codegen/src/machinst/abi.rs
@@ -133,12 +133,11 @@ pub trait ABICall {
     fn num_args(&self) -> usize;
 
     /// Copy an argument value from a source register, prior to the call.
-    fn gen_copy_reg_to_arg(
+    fn gen_copy_reg_to_arg<C: LowerCtx<I = Self::I>>(
         &self,
+        ctx: &mut C,
         idx: usize,
         from_reg: Reg,
-        tmp1: Writable<Reg>,
-        tmp2: Writable<Reg>,
     ) -> Vec<Self::I>;
 
     /// Copy a return value into a destination register, after the call returns.