cranelift: Fix spillslot regression on big-endian platforms

PR 2840 changed the store_spillslot routine to always store
integer registers in full word size to a spill slot.  However,
the load_spillslot routine was not updated, which may causes
the contents to be reloaded in a different type.  On big-endian
systems this will fetch wrong data.

Fixed by using the same type override in load_spillslot.

cranelift/filetests/filetests/isa/x64/store-stack-full-width-i32.clif

@@ -51,7 +51,7 @@ block0(v0: i32, v1: i32, v2: i32):
 ;; This should be movq below, not movl.
 ; nextln:  movq    %rsi, rsp(0 + virtual offset)
 
-; nextln:  movslq  rsp(0 + virtual offset), %rsi
+; nextln:  movq    rsp(0 + virtual offset), %rsi
 ; nextln:  addl    %edi, %esi
 
     ;; Put an effectful instruction so that the live-ranges of the adds and