From 10efe8e780c9276e79a0bb8f8afb293e67b8f846 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Thu, 15 Apr 2021 20:35:42 +0200 Subject: [PATCH] cranelift: Fix spillslot regression on big-endian platforms PR 2840 changed the store_spillslot routine to always store integer registers in full word size to a spill slot. However, the load_spillslot routine was not updated, which may causes the contents to be reloaded in a different type. On big-endian systems this will fetch wrong data. Fixed by using the same type override in load_spillslot. --- cranelift/codegen/src/machinst/abi_impl.rs | 9 +++++++++ .../filetests/isa/x64/store-stack-full-width-i32.clif | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/cranelift/codegen/src/machinst/abi_impl.rs b/cranelift/codegen/src/machinst/abi_impl.rs index 925ee8bf6d..56ebec48f0 100644 --- a/cranelift/codegen/src/machinst/abi_impl.rs +++ b/cranelift/codegen/src/machinst/abi_impl.rs @@ -1209,6 +1209,15 @@ impl ABICallee for ABICalleeImpl { let spill_off = islot * M::word_bytes() as i64; let sp_off = self.stackslots_size as i64 + spill_off; trace!("load_spillslot: slot {:?} -> sp_off {}", slot, sp_off); + + // Integer types smaller than word size have been spilled as words below, + // and therefore must be reloaded in the same type. + let ty = if ty.is_int() && ty.bytes() < M::word_bytes() { + M::word_type() + } else { + ty + }; + gen_load_stack_multi::(StackAMode::NominalSPOffset(sp_off, ty), into_regs, ty) } diff --git a/cranelift/filetests/filetests/isa/x64/store-stack-full-width-i32.clif b/cranelift/filetests/filetests/isa/x64/store-stack-full-width-i32.clif index 10b3102c17..31edd7bdca 100644 --- a/cranelift/filetests/filetests/isa/x64/store-stack-full-width-i32.clif +++ b/cranelift/filetests/filetests/isa/x64/store-stack-full-width-i32.clif @@ -51,7 +51,7 @@ block0(v0: i32, v1: i32, v2: i32): ;; This should be movq below, not movl. ; nextln: movq %rsi, rsp(0 + virtual offset) -; nextln: movslq rsp(0 + virtual offset), %rsi +; nextln: movq rsp(0 + virtual offset), %rsi ; nextln: addl %edi, %esi ;; Put an effectful instruction so that the live-ranges of the adds and