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Lint fixes (#99)

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* Replace a single-character string literal with a character literal.

* Use is_some() instead of comparing with Some(_).

* Add code-quotes around type names in comments.

* Use !...is_empty() instead of len() != 0.

* Tidy up redundant returns.

* Remove redundant .clone() calls.

* Remove unnecessary explicit lifetime parameters.

* Tidy up unnecessary '&'s.

* Add parens to make operator precedence explicit.

* Use debug_assert_eq instead of debug_assert with ==.

* Replace a &Vec argument with a &[...].

* Replace `a = a op b` with `a op= b`.

* Avoid unnecessary closures.

* Avoid .iter() and .iter_mut() for iterating over containers.

* Remove unneeded qualification.
This commit is contained in:
Dan Gohman
2017-06-19 16:24:10 -07:00
committed by Jakob Stoklund Olesen
parent 3693735874
commit 0c7316ae28
24 changed files with 132 additions and 137 deletions
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52
lib/cretonne/src/ir/condcodes.rs
View File

@@ -88,17 +88,17 @@ impl CondCode for IntCC {
impl Display for IntCC {
fn fmt(&self, f: &mut Formatter) -> fmt::Result {
use self::IntCC::*;
f.write_str(match self {
&Equal => "eq",
&NotEqual => "ne",
&SignedGreaterThan => "sgt",
&SignedGreaterThanOrEqual => "sge",
&SignedLessThan => "slt",
&SignedLessThanOrEqual => "sle",
&UnsignedGreaterThan => "ugt",
&UnsignedGreaterThanOrEqual => "uge",
&UnsignedLessThan => "ult",
&UnsignedLessThanOrEqual => "ule",
f.write_str(match *self {
Equal => "eq",
NotEqual => "ne",
SignedGreaterThan => "sgt",
SignedGreaterThanOrEqual => "sge",
SignedLessThan => "slt",
SignedLessThanOrEqual => "sle",
UnsignedGreaterThan => "ugt",
UnsignedGreaterThanOrEqual => "uge",
UnsignedLessThan => "ult",
UnsignedLessThanOrEqual => "ule",
})
}
}
@@ -219,21 +219,21 @@ impl CondCode for FloatCC {
impl Display for FloatCC {
fn fmt(&self, f: &mut Formatter) -> fmt::Result {
use self::FloatCC::*;
f.write_str(match self {
&Ordered => "ord",
&Unordered => "uno",
&Equal => "eq",
&NotEqual => "ne",
&OrderedNotEqual => "one",
&UnorderedOrEqual => "ueq",
&LessThan => "lt",
&LessThanOrEqual => "le",
&GreaterThan => "gt",
&GreaterThanOrEqual => "ge",
&UnorderedOrLessThan => "ult",
&UnorderedOrLessThanOrEqual => "ule",
&UnorderedOrGreaterThan => "ugt",
&UnorderedOrGreaterThanOrEqual => "uge",
f.write_str(match *self {
Ordered => "ord",
Unordered => "uno",
Equal => "eq",
NotEqual => "ne",
OrderedNotEqual => "one",
UnorderedOrEqual => "ueq",
LessThan => "lt",
LessThanOrEqual => "le",
GreaterThan => "gt",
GreaterThanOrEqual => "ge",
UnorderedOrLessThan => "ult",
UnorderedOrLessThanOrEqual => "ule",
UnorderedOrGreaterThan => "ugt",
UnorderedOrGreaterThanOrEqual => "uge",
})
}
}

13
lib/cretonne/src/ir/dfg.rs
View File

@@ -247,10 +247,11 @@ impl DataFlowGraph {
// Try to create short alias chains by finding the original source value.
// This also avoids the creation of loops.
let original = self.resolve_aliases(src);
assert!(dest != original,
"Aliasing {} to {} would create a loop",
dest,
src);
assert_ne!(dest,
original,
"Aliasing {} to {} would create a loop",
dest,
src);
let ty = self.value_type(original);
assert_eq!(self.value_type(dest),
ty,
@@ -326,8 +327,8 @@ pub enum ValueDef {
impl ValueDef {
/// Unwrap the instruction where the value was defined, or panic.
pub fn unwrap_inst(&self) -> Inst {
match self {
&ValueDef::Res(inst, _) => inst,
match *self {
ValueDef::Res(inst, _) => inst,
_ => panic!("Value is not an instruction result"),
}
}

2
lib/cretonne/src/ir/extfunc.rs
View File

@@ -70,7 +70,7 @@ impl Signature {
pub struct DisplaySignature<'a>(&'a Signature, Option<&'a RegInfo>);
fn write_list(f: &mut fmt::Formatter,
args: &Vec<ArgumentType>,
args: &[ArgumentType],
regs: Option<&RegInfo>)
-> fmt::Result {
match args.split_first() {

4
lib/cretonne/src/ir/immediates.rs
View File

@@ -314,7 +314,7 @@ fn format_float(bits: u64, w: u8, t: u8, f: &mut Formatter) -> fmt::Result {
let max_e_bits = (1u64 << w) - 1;
let t_bits = bits & ((1u64 << t) - 1); // Trailing significand.
let e_bits = (bits >> t) & max_e_bits; // Biased exponent.
let sign_bit = (bits >> w + t) & 1;
let sign_bit = (bits >> (w + t)) & 1;
let bias: i32 = (1 << (w - 1)) - 1;
let e = e_bits as i32 - bias; // Unbiased exponent.
@@ -381,7 +381,7 @@ fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
debug_assert!((t + w + 1).is_power_of_two(), "Unexpected IEEE format size");
let (sign_bit, s2) = if s.starts_with('-') {
(1u64 << t + w, &s[1..])
(1u64 << (t + w), &s[1..])
} else if s.starts_with('+') {
(0, &s[1..])
} else {

28
lib/cretonne/src/ir/instructions.rs
View File

@@ -286,23 +286,23 @@ impl InstructionData {
/// Any instruction that can transfer control to another EBB reveals its possible destinations
/// here.
pub fn analyze_branch<'a>(&'a self, pool: &'a ValueListPool) -> BranchInfo<'a> {
match self {
&InstructionData::Jump {
match *self {
InstructionData::Jump {
destination,
ref args,
..
} => BranchInfo::SingleDest(destination, &args.as_slice(pool)),
&InstructionData::Branch {
} => BranchInfo::SingleDest(destination, args.as_slice(pool)),
InstructionData::Branch {
destination,
ref args,
..
} => BranchInfo::SingleDest(destination, &args.as_slice(pool)[1..]),
&InstructionData::BranchIcmp {
InstructionData::BranchIcmp {
destination,
ref args,
..
} => BranchInfo::SingleDest(destination, &args.as_slice(pool)[2..]),
&InstructionData::BranchTable { table, .. } => BranchInfo::Table(table),
InstructionData::BranchTable { table, .. } => BranchInfo::Table(table),
_ => BranchInfo::NotABranch,
}
}
@@ -312,10 +312,10 @@ impl InstructionData {
///
/// Multi-destination branches like `br_table` return `None`.
pub fn branch_destination(&self) -> Option<Ebb> {
match self {
&InstructionData::Jump { destination, .. } => Some(destination),
&InstructionData::Branch { destination, .. } => Some(destination),
&InstructionData::BranchIcmp { destination, .. } => Some(destination),
match *self {
InstructionData::Jump { destination, .. } => Some(destination),
InstructionData::Branch { destination, .. } => Some(destination),
InstructionData::BranchIcmp { destination, .. } => Some(destination),
_ => None,
}
}
@@ -337,11 +337,11 @@ impl InstructionData {
///
/// Any instruction that can call another function reveals its call signature here.
pub fn analyze_call<'a>(&'a self, pool: &'a ValueListPool) -> CallInfo<'a> {
match self {
&InstructionData::Call { func_ref, ref args, .. } => {
CallInfo::Direct(func_ref, &args.as_slice(pool))
match *self {
InstructionData::Call { func_ref, ref args, .. } => {
CallInfo::Direct(func_ref, args.as_slice(pool))
}
&InstructionData::IndirectCall { sig_ref, ref args, .. } => {
InstructionData::IndirectCall { sig_ref, ref args, .. } => {
CallInfo::Indirect(sig_ref, &args.as_slice(pool)[1..])
}
_ => CallInfo::NotACall,

2
lib/cretonne/src/ir/jumptable.rs
View File

@@ -65,7 +65,7 @@ impl JumpTableData {
/// Enumerate over all `(idx, dest)` pairs in the table in order.
///
/// This returns an iterator that skips any empty slots in the table.
pub fn entries<'a>(&'a self) -> Entries {
pub fn entries(&self) -> Entries {
Entries(self.table.iter().cloned().enumerate())
}

8
lib/cretonne/src/ir/valueloc.rs
View File

@@ -98,16 +98,16 @@ impl Default for ArgumentLoc {
impl ArgumentLoc {
/// Is this an assigned location? (That is, not `Unassigned`).
pub fn is_assigned(&self) -> bool {
match self {
&ArgumentLoc::Unassigned => false,
match *self {
ArgumentLoc::Unassigned => false,
_ => true,
}
}
/// Is this a register location?
pub fn is_reg(&self) -> bool {
match self {
&ArgumentLoc::Reg(_) => true,
match *self {
ArgumentLoc::Reg(_) => true,
_ => false,
}
}