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Merge pull request #3027 from afonso360/aarch64-i128-select

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aarch64: Implement lowering i128 select
This commit is contained in:
Chris Fallin
2021-06-24 11:25:18 -07:00
committed by GitHub
parent 8172620763 7a5948f729
commit 0c0a94155e
3 changed files with 60 additions and 11 deletions
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39
cranelift/codegen/src/isa/aarch64/lower_inst.rs
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@@ -1691,20 +1691,37 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
};
// csel.cond rd, rn, rm
let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
let rm = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
let ty = ctx.output_ty(insn, 0);
let bits = ty_bits(ty);
let is_float = ty_has_float_or_vec_representation(ty);
if is_float && bits == 32 {
ctx.emit(Inst::FpuCSel32 { cond, rd, rn, rm });
} else if is_float && bits == 64 {
ctx.emit(Inst::FpuCSel64 { cond, rd, rn, rm });
} else if is_float && bits == 128 {
ctx.emit(Inst::VecCSel { cond, rd, rn, rm });
} else {
ctx.emit(Inst::CSel { cond, rd, rn, rm });
let dst = get_output_reg(ctx, outputs[0]);
let lhs = put_input_in_regs(ctx, inputs[1]);
let rhs = put_input_in_regs(ctx, inputs[2]);
let rd = dst.regs()[0];
let rn = lhs.regs()[0];
let rm = rhs.regs()[0];
match (is_float, bits) {
(true, 32) => ctx.emit(Inst::FpuCSel32 { cond, rd, rn, rm }),
(true, 64) => ctx.emit(Inst::FpuCSel64 { cond, rd, rn, rm }),
(true, 128) => ctx.emit(Inst::VecCSel { cond, rd, rn, rm }),
(false, 128) => {
ctx.emit(Inst::CSel {
cond,
rd: dst.regs()[0],
rn: lhs.regs()[0],
rm: rhs.regs()[0],
});
ctx.emit(Inst::CSel {
cond,
rd: dst.regs()[1],
rn: lhs.regs()[1],
rm: rhs.regs()[1],
});
}
(_, _) => ctx.emit(Inst::CSel { cond, rd, rn, rm }),
}
}

11
cranelift/filetests/filetests/isa/aarch64/condops.clif
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@@ -53,3 +53,14 @@ block0(v0: i32, v1: i8, v2: i8):
; check: subs wzr, w0, #42
; nextln: csel x0, x1, x2, eq
function %i128_select(b1, i128, i128) -> i128 {
block0(v0: b1, v1: i128, v2: i128):
v3 = select.i128 v0, v1, v2
return v3
}
; check: subs wzr, w0, wzr
; nextln: csel x0, x2, x4, ne
; nextln: csel x1, x3, x5, ne

21
cranelift/filetests/filetests/runtests/i128-select.clif Normal file
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@@ -0,0 +1,21 @@
test run
target aarch64
target x86_64 machinst
function %i128_select(i8, i64, i64, i64, i64) -> i64, i64 {
block0(v0: i8, v1: i64, v2: i64, v3: i64, v4: i64):
v5 = icmp_imm ne v0, 0
v6 = iconcat v1, v2
v7 = iconcat v3, v4
v8 = select.i128 v5, v6, v7
v9, v10 = isplit v8
return v9, v10
}
; run: %i128_select(1, 0, 0, 1, 1) == [0, 0]
; run: %i128_select(0, 0, 0, 1, 1) == [1, 1]
; run: %i128_select(1, 1, 2, 3, 4) == [1, 2]
; run: %i128_select(0, 1, 2, 3, 4) == [3, 4]