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Add x64 lowering of Clif flt load instruction for new backend

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Adds support for the clif flt load instruction.
This commit is contained in:
Johnnie Birch
2020-06-26 14:34:42 -07:00
parent f2dd1535d5
commit 0aa56c500c
2 changed files with 13 additions and 2 deletions
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8
cranelift/codegen/src/isa/x64/inst/emit_tests.rs
View File

@@ -77,7 +77,7 @@ fn test_x64_emit() {
let _w_xmm6 = Writable::<Reg>::from_reg(xmm6); let _w_xmm6 = Writable::<Reg>::from_reg(xmm6);
let w_xmm7 = Writable::<Reg>::from_reg(xmm7); let w_xmm7 = Writable::<Reg>::from_reg(xmm7);
let w_xmm8 = Writable::<Reg>::from_reg(xmm8); let w_xmm8 = Writable::<Reg>::from_reg(xmm8);
let _w_xmm9 = Writable::<Reg>::from_reg(xmm9); let w_xmm9 = Writable::<Reg>::from_reg(xmm9);
let w_xmm10 = Writable::<Reg>::from_reg(xmm10); let w_xmm10 = Writable::<Reg>::from_reg(xmm10);
let w_xmm11 = Writable::<Reg>::from_reg(xmm11); let w_xmm11 = Writable::<Reg>::from_reg(xmm11);
let w_xmm12 = Writable::<Reg>::from_reg(xmm12); let w_xmm12 = Writable::<Reg>::from_reg(xmm12);
@@ -2701,6 +2701,12 @@ fn test_x64_emit() {
"movss %xmm15, 128(%r12)", "movss %xmm15, 128(%r12)",
)); ));
insns.push((
Inst::xmm_mov_rm_r(SseOpcode::Movd, RegMem::mem(Amode::imm_reg(2, r10)), w_xmm9),
"66450F6E4A02",
"movd 2(%r10), %xmm9",
));
insns.push(( insns.push((
Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4), Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4),
"0F56E5", "0F56E5",

7
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -513,7 +513,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) -> Codeg
ctx.emit(Inst::movzx_rm_r(ext_mode.unwrap(), RegMem::mem(addr), dst)) ctx.emit(Inst::movzx_rm_r(ext_mode.unwrap(), RegMem::mem(addr), dst))
} }
} }
(_, true) => unimplemented!("FPU loads"), (_, true) => {
ctx.emit(match elem_ty {
F32 => Inst::xmm_mov_rm_r(SseOpcode::Movd, RegMem::mem(addr), dst),
_ => unimplemented!("FP load not 32-bit"),
});
}
} }
} }