diff --git a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
index fc77fde871..96f350d43d 100644
--- a/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/x64/inst/emit_tests.rs
@@ -77,7 +77,7 @@ fn test_x64_emit() {
     let _w_xmm6 = Writable::<Reg>::from_reg(xmm6);
     let w_xmm7 = Writable::<Reg>::from_reg(xmm7);
     let w_xmm8 = Writable::<Reg>::from_reg(xmm8);
-    let _w_xmm9 = Writable::<Reg>::from_reg(xmm9);
+    let w_xmm9 = Writable::<Reg>::from_reg(xmm9);
     let w_xmm10 = Writable::<Reg>::from_reg(xmm10);
     let w_xmm11 = Writable::<Reg>::from_reg(xmm11);
     let w_xmm12 = Writable::<Reg>::from_reg(xmm12);
@@ -2701,6 +2701,12 @@ fn test_x64_emit() {
         "movss   %xmm15, 128(%r12)",
     ));
 
+    insns.push((
+        Inst::xmm_mov_rm_r(SseOpcode::Movd, RegMem::mem(Amode::imm_reg(2, r10)), w_xmm9),
+        "66450F6E4A02",
+        "movd    2(%r10), %xmm9",
+    ));
+
     insns.push((
         Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4),
         "0F56E5",
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 081617f805..24e3752895 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -513,7 +513,12 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) -> Codeg
                         ctx.emit(Inst::movzx_rm_r(ext_mode.unwrap(), RegMem::mem(addr), dst))
                     }
                 }
-                (_, true) => unimplemented!("FPU loads"),
+                (_, true) => {
+                    ctx.emit(match elem_ty {
+                        F32 => Inst::xmm_mov_rm_r(SseOpcode::Movd, RegMem::mem(addr), dst),
+                        _ => unimplemented!("FP load not 32-bit"),
+                    });
+                }
             }
         }