Compute top-level register classes for each register bank.

A top-level register class is one that has no sub-classes. It is
possible to have multiple top-level register classes in the same
register bank. For example, ARM's FPR bank has both D and Q top-level
register classes.

Number register classes such that all top-level register classes appear
as a contiguous sequence starting from 0. This will be used by the
register allocator when counting used registers per top-level register
class.

lib/cretonne/src/isa/registers.rs

@@ -42,6 +42,15 @@ pub struct RegBank {
     /// The remaining register units will be named this prefix followed by their decimal offset in
     /// the bank. So with a prefix `r`, registers will be named `r8`, `r9`, ...
     pub prefix: &'static str,
+
+    /// Index of the first top-level register class in this bank.
+    pub first_toprc: usize,
+
+    /// Number of top-level register classes in this bank.
+    ///
+    /// The top-level register classes in a bank are guaranteed to be numbered sequentially from
+    /// `first_toprc`, and all top-level register classes across banks come before any sub-classes.
+    pub num_toprcs: usize,
 }
 
 impl RegBank {
@@ -111,6 +120,9 @@ pub struct RegClassData {
     /// Index of the register bank this class belongs to.
     pub bank: u8,
 
+    /// Index of the top-level register class contains this one.
+    pub toprc: u8,
+
     /// The first register unit in this class.
     pub first: RegUnit,
 

lib/cretonne/src/regalloc/allocatable_set.rs

@@ -141,6 +141,7 @@ mod tests {
         index: 0,
         width: 1,
         bank: 0,
+        toprc: 0,
         first: 28,
         subclasses: 0,
         mask: [0xf0000000, 0x0000000f, 0],
@@ -150,6 +151,7 @@ mod tests {
         index: 0,
         width: 2,
         bank: 0,
+        toprc: 0,
         first: 28,
         subclasses: 0,
         mask: [0x50000000, 0x0000000a, 0],