Add controls for enabling M, F, and D RISC-V extensions.

Three predicates affect each extension:

- supports_m determines whether the target CPU supports the instruction set.
- enable_m determines if the instructions should be used, assuming they're
  available.
- use_m is the predicate used to actually use the instructions.

meta/cretonne/settings.py

@@ -20,8 +20,16 @@ opt_level = EnumSetting(
 
 is_64bit = BoolSetting("Enable 64-bit code generation")
 
+enable_float = BoolSetting(
+        """Enable the use of floating-point instructions""",
+        default=True)
+
 enable_simd = BoolSetting(
         """Enable the use of SIMD instructions.""",
         default=True)
 
+enable_atomics = BoolSetting(
+        """Enable the use of atomic instructions""",
+        default=True)
+
 group.close(globals())

meta/isa/riscv/settings.py

@@ -14,6 +14,15 @@ supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
 supports_f = BoolSetting("CPU supports the 'F' extension (float)")
 supports_d = BoolSetting("CPU supports the 'D' extension (double)")
 
+enable_m = BoolSetting(
+        "Enable the use of 'M' instructions if available",
+        default=True)
+
+use_m = And(supports_m, enable_m)
+use_a = And(supports_a, shared.enable_atomics)
+use_f = And(supports_f, shared.enable_float)
+use_d = And(supports_d, shared.enable_float)
+
 full_float = And(shared.enable_simd, supports_f, supports_d)
 
 isa.settings.close(globals())