From 09734f203375a4a57b7f65d0704ea9caa06850e0 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Tue, 30 Aug 2016 15:10:38 -0700
Subject: [PATCH] Add controls for enabling M, F, and D RISC-V extensions.

Three predicates affect each extension:

- supports_m determines whether the target CPU supports the instruction set.
- enable_m determines if the instructions should be used, assuming they're
  available.
- use_m is the predicate used to actually use the instructions.
---
 cranelift/src/libcretonne/isa/riscv/settings.rs | 3 ++-
 cranelift/src/libcretonne/settings.rs           | 4 +++-
 meta/cretonne/settings.py                       | 8 ++++++++
 meta/isa/riscv/settings.py                      | 9 +++++++++
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/cranelift/src/libcretonne/isa/riscv/settings.rs b/cranelift/src/libcretonne/isa/riscv/settings.rs
index 1dd1adc405..ae765d9c15 100644
--- a/cranelift/src/libcretonne/isa/riscv/settings.rs
+++ b/cranelift/src/libcretonne/isa/riscv/settings.rs
@@ -22,7 +22,8 @@ mod tests {
                     supports_m = false\n\
                     supports_a = false\n\
                     supports_f = false\n\
-                    supports_d = false\n");
+                    supports_d = false\n\
+                    enable_m = true\n");
         // Predicates are not part of the Display output.
         assert_eq!(f.full_float(), false);
     }
diff --git a/cranelift/src/libcretonne/settings.rs b/cranelift/src/libcretonne/settings.rs
index c4f42d4a04..c7c0d1eb30 100644
--- a/cranelift/src/libcretonne/settings.rs
+++ b/cranelift/src/libcretonne/settings.rs
@@ -261,7 +261,9 @@ mod tests {
                    "[shared]\n\
                     opt_level = \"default\"\n\
                     is_64bit = false\n\
-                    enable_simd = true\n");
+                    enable_float = true\n\
+                    enable_simd = true\n\
+                    enable_atomics = true\n");
         assert_eq!(f.opt_level(), super::OptLevel::Default);
         assert_eq!(f.enable_simd(), true);
     }
diff --git a/meta/cretonne/settings.py b/meta/cretonne/settings.py
index 4147d5a514..522a649ef3 100644
--- a/meta/cretonne/settings.py
+++ b/meta/cretonne/settings.py
@@ -20,8 +20,16 @@ opt_level = EnumSetting(
 
 is_64bit = BoolSetting("Enable 64-bit code generation")
 
+enable_float = BoolSetting(
+        """Enable the use of floating-point instructions""",
+        default=True)
+
 enable_simd = BoolSetting(
         """Enable the use of SIMD instructions.""",
         default=True)
 
+enable_atomics = BoolSetting(
+        """Enable the use of atomic instructions""",
+        default=True)
+
 group.close(globals())
diff --git a/meta/isa/riscv/settings.py b/meta/isa/riscv/settings.py
index 1ab2917036..8aae295342 100644
--- a/meta/isa/riscv/settings.py
+++ b/meta/isa/riscv/settings.py
@@ -14,6 +14,15 @@ supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
 supports_f = BoolSetting("CPU supports the 'F' extension (float)")
 supports_d = BoolSetting("CPU supports the 'D' extension (double)")
 
+enable_m = BoolSetting(
+        "Enable the use of 'M' instructions if available",
+        default=True)
+
+use_m = And(supports_m, enable_m)
+use_a = And(supports_a, shared.enable_atomics)
+use_f = And(supports_f, shared.enable_float)
+use_d = And(supports_d, shared.enable_float)
+
 full_float = And(shared.enable_simd, supports_f, supports_d)
 
 isa.settings.close(globals())