Add controls for enabling M, F, and D RISC-V extensions.

Three predicates affect each extension:

- supports_m determines whether the target CPU supports the instruction set.
- enable_m determines if the instructions should be used, assuming they're
  available.
- use_m is the predicate used to actually use the instructions.

cranelift/src/libcretonne/isa/riscv/settings.rs

@@ -22,7 +22,8 @@ mod tests {
                     supports_m = false\n\
                     supports_a = false\n\
                     supports_f = false\n\
-                    supports_d = false\n");
+                    supports_d = false\n\
+                    enable_m = true\n");
         // Predicates are not part of the Display output.
         assert_eq!(f.full_float(), false);
     }

cranelift/src/libcretonne/settings.rs

@@ -261,7 +261,9 @@ mod tests {
                    "[shared]\n\
                     opt_level = \"default\"\n\
                     is_64bit = false\n\
-                    enable_simd = true\n");
+                    enable_float = true\n\
+                    enable_simd = true\n\
+                    enable_atomics = true\n");
         assert_eq!(f.opt_level(), super::OptLevel::Default);
         assert_eq!(f.enable_simd(), true);
     }