Define register classes for 4 ISAs.

lib/cretonne/meta/isa/arm32/registers.py

@@ -2,7 +2,7 @@
 ARM32 register banks.
 """
 from __future__ import absolute_import
-from cdsl.registers import RegBank
+from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
@@ -27,3 +27,8 @@ FloatRegs = RegBank(
         - Q registers are 4 units each.
         """,
         units=64, prefix='s')
+
+GPR = RegClass('GPR', IntRegs)
+S = RegClass('S', FloatRegs, count=32)
+D = RegClass('D', FloatRegs, width=2)
+Q = RegClass('Q', FloatRegs, width=4)

lib/cretonne/meta/isa/arm64/registers.py

@@ -2,7 +2,7 @@
 Aarch64 register banks.
 """
 from __future__ import absolute_import
-from cdsl.registers import RegBank
+from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
@@ -17,3 +17,6 @@ FloatRegs = RegBank(
         'FloatRegs', ISA,
         'Floating point registers',
         units=32, prefix='v')
+
+GPR = RegClass('GPR', IntRegs)
+FPR = RegClass('FPR', FloatRegs)

lib/cretonne/meta/isa/intel/registers.py

@@ -23,7 +23,7 @@ data types, and the H-registers even less so. Rather than trying to model the
 H-registers accurately, we'll avoid using them in both I32 and I64 modes.
 """
 from __future__ import absolute_import
-from cdsl.registers import RegBank
+from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
@@ -37,3 +37,6 @@ FloatRegs = RegBank(
         'FloatRegs', ISA,
         'SSE floating point registers',
         units=16, prefix='xmm')
+
+GPR = RegClass('GPR', IntRegs)
+FPR = RegClass('FPR', FloatRegs)

lib/cretonne/meta/isa/riscv/registers.py

@@ -2,7 +2,7 @@
 RISC-V register banks.
 """
 from __future__ import absolute_import
-from cdsl.registers import RegBank
+from cdsl.registers import RegBank, RegClass
 from .defs import ISA
 
 
@@ -16,3 +16,6 @@ FloatRegs = RegBank(
         'FloatRegs', ISA,
         'Floating point registers',
         units=32, prefix='f')
+
+GPR = RegClass('GPR', IntRegs)
+FPR = RegClass('FPR', FloatRegs)