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wasmtime/lib/cretonne/meta/isa/riscv/registers.py
2016-11-11 15:08:12 -08:00

22 lines
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Python

"""
RISC-V register banks.
"""
from __future__ import absolute_import
from cdsl.registers import RegBank, RegClass
from .defs import ISA
# We include `x0`, a.k.a `zero` in the register bank. It will be reserved.
IntRegs = RegBank(
'IntRegs', ISA,
'General purpose registers',
units=32, prefix='x')
FloatRegs = RegBank(
'FloatRegs', ISA,
'Floating point registers',
units=32, prefix='f')
GPR = RegClass('GPR', IntRegs)
FPR = RegClass('FPR', FloatRegs)