Add Intel encodings for imul.

lib/cretonne/meta/isa/intel/encodings.py

@@ -23,6 +23,11 @@ for inst,           opc in [
     # default. Otherwise reg-alloc would never use r8 and up.
     I64.enc(inst.i32, *r.rr(opc))
 
+I32.enc(base.imul.i32, *r.rrx(0x0f, 0xaf))
+I64.enc(base.imul.i64, *r.rrx.rex(0x0f, 0xaf, w=1))
+I64.enc(base.imul.i32, *r.rrx.rex(0x0f, 0xaf))
+I64.enc(base.imul.i32, *r.rrx(0x0f, 0xaf))
+
 I32.enc(base.copy.i32, *r.umr(0x89))
 I64.enc(base.copy.i64, *r.umr.rex(0x89, w=1))
 I64.enc(base.copy.i32, *r.umr.rex(0x89))

lib/cretonne/meta/isa/intel/recipes.py

@@ -197,6 +197,14 @@ rr = TailRecipe(
         modrm_rr(in_reg0, in_reg1, sink);
         ''')
 
+# XX /r with operands swapped. (RM form).
+rrx = TailRecipe(
+        'rrx', Binary, size=1, ins=(GPR, GPR), outs=0,
+        emit='''
+        PUT_OP(bits, rex2(in_reg1, in_reg0), sink);
+        modrm_rr(in_reg1, in_reg0, sink);
+        ''')
+
 # XX /r, but for a unary operator with separate input/output register, like
 # copies. MR form.
 umr = TailRecipe(

lib/cretonne/src/isa/intel/binemit.rs

@@ -76,6 +76,14 @@ fn put_op2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     sink.put1(bits as u8);
 }
 
+// Emit two-byte opcode: 0F XX with REX prefix.
+fn put_rexop2<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
+    debug_assert_eq!(bits & 0x0f00, 0x0400, "Invalid encoding bits for RexOp2*");
+    rex_prefix(bits, rex, sink);
+    sink.put1(0x0f);
+    sink.put1(bits as u8);
+}
+
 // Emit single-byte opcode with mandatory prefix.
 fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, rex: u8, sink: &mut CS) {
     debug_assert_eq!(bits & 0x8c00, 0, "Invalid encoding bits for Mp1*");