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d67eb93148e68c05618ae131f56b30f16b7408eb
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40 Commits

Author SHA1 Message Date
Alexis Engelke
c99e860a5e tests: Add few more encode/decode cases 2021-04-02 11:28:13 +02:00
Alexis Engelke
0521ff7d42 decode: Fix VBLENDVP[SD] opcodes 2021-03-23 12:52:37 +01:00
Alexis Engelke
4f2366afd1 instrs: Add VIA PadLock and AMD RDPRU 2021-01-23 16:47:30 +01:00
Alexis Engelke
f7567c89bd instrs: Fix VMOVSS/VMOVSD with memory operand 2021-01-23 16:44:16 +01:00
Alexis Engelke
d7b9c97681 instrs: Remove MPX instructions 
These instructions have plenty of corner cases and some instructions
have a different usage of the memory operand. Given that MPX is already
deprecated by Intel, it seems that the better option is to decode these
(rarely occuring) instructions as NOPs.
 2021-01-23 16:18:12 +01:00
Alexis Engelke
103fc536b0 instrs: Fix operands of VRCPPS/VSQRTP[SD]/VRSQRTPS 2021-01-23 14:39:48 +01:00
Alexis Engelke
f17d84cee6 format: Emit XACQUIRE/XRELEASE 
As CMPXCHGD has a mandatory prefix table, it is absolutely necessary
that the presence of any tables does not modify any decoding state.
 2021-01-23 14:35:08 +01:00
Alexis Engelke
ab63a3c921 instrs: Fix mandatory prefixes of CMPXCHG8B/16B 2021-01-23 14:30:45 +01:00
Alexis Engelke
7919b8115a format: Emit REP/REPNZ only for string instruction 2021-01-23 14:29:29 +01:00
Alexis Engelke
fe68dbb743 decode: Fix LOCK handling for MOV CR/DR 2021-01-23 14:28:27 +01:00
Alexis Engelke
85fdaa3a9b instrs: Remove incorrect NFx specifiers 
The new trie implementation is more flexible and allows omitting
prefixes even with a ModRM specifier in the opcode. Use this flexibility
to simplify instruction descriptions.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
9d7b584121 decode: Verify 3DNow! opcode validity 2021-01-10 18:53:32 +01:00
Alexis Engelke
80df5ff47c instrs: Add reserved NOP/PREFETCH as weak opcodes 2021-01-10 16:53:27 +01:00
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
111769832f format: Properly output VSIB encodings 2021-01-08 10:37:13 +01:00
Alexis Engelke
44808e7b1a format: Format instructions with Intel syntax 2021-01-03 21:18:57 +01:00
Alexis Engelke
d8c7ee94b7 instrs: Minor fixes to operand sizes 2021-01-03 20:08:34 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
8976c7141a decode: Fix erroneous decoding of high-byte regs 2020-11-28 13:54:19 +01:00
Alexis Engelke
bb8510d77f decode: Ignore ES/CS/SS/DS override in 64-bit mode 2020-11-22 20:59:13 +01:00
Alexis Engelke
ad1f1e39c3 decode: Minor non-functional changes 2020-11-22 15:14:57 +01:00
Alexis Engelke
6fe5500444 instrs: Force RIP access to 64-bit and fix XBEGIN 2020-11-22 15:13:52 +01:00
Alexis Engelke
bbc3b34f71 decode: Fix VEX + REX + legacy combinations 2020-11-21 15:43:51 +01:00
Alexis Engelke
7f0bd4de8b decode: Fix combinations of VEX with legacy prefix 2020-11-21 14:59:25 +01:00
Alexis Engelke
95070908d0 tests/decode: Add more test cases 2020-11-09 09:47:36 +01:00
Alexis Engelke
58464d6fa1 decode: Fix ignoring VEX.B in 32-bit mode 2020-11-09 09:47:36 +01:00
Alexis Engelke
2e7e396325 decode: Remove TABLE_PREFIX_REP and use NFx prefix 2020-11-09 09:47:36 +01:00
Alexis Engelke
4e95c8d152 instrs: Several operand size and AVX-related fixes 2020-07-05 14:59:24 +02:00
Alexis Engelke
dc668691d8 instrs: Specify segment register size 2020-07-04 14:25:22 +02:00
Alexis Engelke
da4ad137d8 instrs: Remove redundant IMM_8 2020-07-04 08:55:51 +02:00
Alexis Engelke
e7b5982ba9 tests/decode: Add CRC32 and MOVBE test cases 2020-06-27 19:01:26 +02:00
Alexis Engelke
ab27ea6338 tests/decode: Print architecture mode on failure 2020-06-27 19:01:26 +02:00
Alexis Engelke
ceea786c7f tests/decode: Rewrite in C, speed-up is >100x 2020-06-27 19:01:26 +02:00