While for almost all instructions the memory address displacement is
sign-extended 32-bits (like for immediate operands), there is a single
case where this is not true: the FD/TD mov encoding allows for a 64-bit
memory address to be specified.
Addresses relative to the actual address of the instruction are decoded
as new offset operand, where the RIP has to be added to obtain the real
value. For backwards compatibility, the new behavior is only exposed if
the address of the instruction is specified as zero.
This was previously needed to distinguish VZEROALL and VZEROUPPER. As
mandatory VEX.L is now handled properly, there is no need to export this
encoding detail any longer.
