T0b1/test-repo
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
331 Commits 1 Branch 0 Tags
955f1390257f1cdc97e636ae9da7efcb34b94ddd
Commit Graph

331 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alexis Engelke
955f139025 instrs: Add AVX512-FP16 instructions 2023-01-15 13:47:11 +01:00
Alexis Engelke
8550e2cac9 parseinstrs: Add support for BCST16 
2-byte broadcasts cannot be inferred from the encoding and need to be
indicated in the descriptor.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
06832825ec fadec: Store broadcast size in segment 
This is a preparation for AVX512-FP16, where the broadcast size is not
just 32/64 bit depending solely on EVEX.W, but can also be 16 bit (with
EVEX.W=0). The broadcast size therefore needs two bits, but the evex
field only had one free bit left. Store broadcast size with the segment
for now. (This is not a good fit and is likely to change at some point.)
 2023-01-15 13:47:11 +01:00
Alexis Engelke
a3c8848005 instrs: Remove unused WIG specifier 
If REX.W/VEX.W/EVEX.W is not used as opcode extension or as operand
size, it is ignored automatically. No need to encode this.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
b1f7a5fe19 decode: Add UD for EVEX.z without EVEX.aaa 
This was tested on hardware, where EVEX.z without EVEX.aaa reliably
causes #UD. The SDM is not too precise about this.
 2023-01-15 13:47:11 +01:00
Alexis Engelke
e04aff73dc decode: Add AVX-512 support 2023-01-15 13:47:11 +01:00
Alexis Engelke
ec5a430b5c decode: Decode EVEX prefix 2023-01-15 13:40:51 +01:00
Alexis Engelke
4a552feabf decode-test: Increase coverage 2023-01-15 13:38:40 +01:00
Alexis Engelke
36c37186dd encode-test: Test all REX/VEX.RXB combinations 2023-01-15 13:38:28 +01:00
Alexis Engelke
7b2a586449 parseinstrs: Fix erroneous 16-bit operand size 2023-01-15 11:24:35 +01:00
Alexis Engelke
d7aff5de28 format: Fix clz for 32-bit targets 2023-01-15 11:09:40 +01:00
Alexis Engelke
2f7e8dd0de encode: Remove descriptor table 
All relevant information is now encoded directly in the numeric value of
the mnemonic, significantly shrinking the size of the encoder.
 2023-01-15 11:09:40 +01:00
Alexis Engelke
9f0ddeb44a encode: Fix [LMS]FENCE encoding 2023-01-13 14:25:55 +01:00
Alexis Engelke
cbbfd9da0e instrs: Fix minor (currently ignored) annotations 2022-12-28 12:28:22 +01:00
Alexis Engelke
36019517cf parseinstrs: Print stats only if not subproject 
Statistics are only interesting for development.
 2022-12-28 12:28:22 +01:00
Alexis Engelke
6bf96d6963 parseinstrs: Improve performance of superstring 
This algorithm yields slightly worse results, but is substantially
faster for larger string counts.
 2022-12-28 12:28:22 +01:00
Alexis Engelke
771d968165 instrs: Fix wrong operand sizes caused by byte imm 2022-12-27 19:46:58 +01:00
Alexis Engelke
377e362a0e decode: Handle imm_byte size differently 
For byte-sized immediates, there are only two options for the operand
size: byte and the instruction's operand size. This knowledge allows to
remove the byte constraint from the set of fixed operand sizes.
 2022-12-27 19:46:04 +01:00
Alexis Engelke
1aec30cd0f instrs: Various small fixes 2022-12-26 22:01:11 +01:00
Alexis Engelke
94fc7a3671 instrs: Fix CLRSSBSY operand size 2022-12-26 19:30:14 +01:00
Alexis Engelke
6a0db935f5 instrs: Remove non-existent VEX-encoded VPSRAVQ 2022-12-26 18:42:15 +01:00
Alexis Engelke
4efe60ffa8 instrs: Fix VMWRITE operand order 2022-12-26 18:42:15 +01:00
Alexis Engelke
e70118a0d7 instrs: Fix VPSRA/VPSRL/VPSLL r/m operand size 2022-12-03 15:06:54 +01:00
Alexis Engelke
003a11ff12 instrs: Fix VMASKMOVDQU encoding 2022-12-03 14:58:06 +01:00
Alexis Engelke
99a9802f50 decode: Store op size per operand type 
This change doesn't really affect performance and is preparatory
work for AVX-512, where the memory operand size is required to compute
the compressed displacement.
 2022-12-03 14:52:06 +01:00
Alexis Engelke
7237391783 tests: Test AVX FMA 2022-11-30 10:01:41 +01:00
Alexis Engelke
0da009862c instrs: Correct PMOV[SZ]X operand size 
Now that we can encode half/fourth/eighth vector size, use it.
 2022-11-30 09:41:12 +01:00
Alexis Engelke
e72e288def tests: Add BMI1 test cases 2022-11-30 09:32:02 +01:00
Alexis Engelke
c54a749713 parseinstrs: Simplify encode opsize derivation 2022-11-30 09:32:02 +01:00
Alexis Engelke
4abad24610 decode: Support half vector size 
This is realized by two changes: first, GP and vector operand size are
completely separated using one extra bit. If the operand size of an
instruction is derived from VEX.L (or EVEX.L'L), then the "opsize" bits
indicate how to derive a smaller vector size (half/quarter/eighth).
 2022-11-30 09:32:02 +01:00
Alexis Engelke
f565f09f9d instrs: Clearly separate vector and GP opsize 
Now, an instruction cannot refer to the GP operand size and the vector
operand size at the same time. This isn't necessary, all necessary
distinguishing could also be achieved manually using W0/W1/66 selectors.
 2022-11-27 18:07:44 +01:00
Alexis Engelke
64f0ae245e instrs: Add AVX-IFMI (VPMADD52[LH]UQ) 2022-11-27 13:39:37 +01:00
Alexis Engelke
e411e1327b instrs: Add AVX-NE-CONVERT instructions 2022-11-27 13:39:37 +01:00
Alexis Engelke
7db75f64d0 instrs: Add VNNI-INT8 and VNNI tests 2022-11-27 13:39:37 +01:00
Alexis Engelke
fe6fe0ffc1 instrs: Add CMPCCXADD 2022-11-27 13:39:37 +01:00
Alexis Engelke
1e0a58a421 instrs: Add RAO-INT (AADD/AAND/AXOR/AOR) 2022-11-27 13:39:37 +01:00
Alexis Engelke
29a62bd1c9 instrs: Add WRMSRNS 2022-11-27 13:39:37 +01:00
Alexis Engelke
769218bbc9 instrs: Add RDMSRLIST/WRMSRLIST 2022-11-27 13:39:37 +01:00
Alexis Engelke
99bea8a81e instrs: Fix VPERMQ and VPERMPD encoding 2022-11-27 13:39:37 +01:00
Alexis Engelke
7142478f41 encode: Fix MVR operand order 2022-11-27 13:39:37 +01:00
Alexis Engelke
d150ccf1a5 instrs: Fix VMI encoding operands and add tests 2022-11-27 13:39:37 +01:00
Alexis Engelke
0e0b03f839 format: Drop fd_strplcpy 2022-11-25 14:58:58 +01:00
Alexis Engelke
6facb5f08c format: Use logarithmic address/operand sizes 
This simplifies register and pointer size formatting.
 2022-11-25 14:50:16 +01:00
Alexis Engelke
1a4eb124a7 fadec: Expose logarithmic sizes 2022-11-25 14:47:58 +01:00
Alexis Engelke
180cc059ed instrs: Fix INVEPT/INVVPID memory operand size 2022-11-25 14:34:57 +01:00
Alexis Engelke
b817713ae8 decode: Store operand size logarithmic 2022-11-25 14:34:22 +01:00
Alexis Engelke
1291603246 decode-test: Add cases for far jmp/ret 2022-11-25 12:38:52 +01:00
Alexis Engelke
1c04ded9b7 decode: Merge zeroreg and vexreg 
There is no instruction that uses an implicit register and an
VEX-encoded register at the same time. Thus, we can merge vexreg and
zeroreg in the instruction descriptor; the zeroreg value will be added
to the vex-operand (which is zero unless set by a VEX prefix).

This also frees 4 descriptor bits for use with AVX-512 (which will
probably need 1-2 additional unused bits, probably from the type).
 2022-11-20 15:25:37 +01:00
Alexis Engelke
19b9d82630 instrs: Add VAES instructions 2022-11-07 08:58:11 +01:00
Alexis Engelke
c15600a1d1 decode-test: Add two more MOVSX cases 2022-11-05 13:56:56 +01:00