Alexis Engelke
24b79f71b6
Add missing FPU instructions
2019-05-05 12:53:29 +02:00
Alexis Engelke
3f278bc6cc
Store register type in decoded instruction
2019-05-05 12:53:10 +02:00
Alexis Engelke
899278600b
Refactor encoding of bit field
2019-05-05 12:26:20 +02:00
Alexis Engelke
dff78c5a86
Support VSIB encoding
2019-04-27 11:16:09 +02:00
Alexis Engelke
1b474a04ac
Add support for missing AVX instructions
2019-04-27 11:10:22 +02:00
Alexis Engelke
a7d4c7be9d
Minor clean-up
2019-04-27 11:09:57 +02:00
Alexis Engelke
db1ec271df
Simplify macros for immediate loading
2019-04-27 08:19:33 +02:00
Alexis Engelke
1ff0e60ddc
Remove unused macros
2019-04-27 08:19:03 +02:00
Alexis Engelke
000349b360
Update README
2019-02-24 17:14:41 +01:00
Alexis Engelke
f4644430b8
Update README
2019-02-24 17:13:56 +01:00
Alexis Engelke
b105c48903
Update README
2019-02-24 17:12:35 +01:00
Alexis Engelke
14c5590413
Set size of rare memory operands to zero
2019-02-24 17:11:32 +01:00
Alexis Engelke
53ca6a2f23
Drop export of VEX.L prefix
...
This was previously needed to distinguish VZEROALL and VZEROUPPER. As
mandatory VEX.L is now handled properly, there is no need to export this
encoding detail any longer.
2019-02-24 15:48:08 +01:00
Alexis Engelke
2dd1c99a81
Fix operand size of some SSE instructions
2019-02-24 15:46:09 +01:00
Alexis Engelke
d5d0009070
Distinguish VZEROALL and VZEROUPPER
2019-02-24 15:45:37 +01:00
Alexis Engelke
f7f0b322c7
Enforce mandatory L0/L1 in VEX prefix
2019-02-24 15:45:00 +01:00
Alexis Engelke
83988828ec
Add some test cases for ModRM decoding
2019-02-24 10:10:02 +01:00
Alexis Engelke
dfd70eef39
Fix bug with VMOV[DQ] operand width in 32-bit mode
2019-02-24 10:09:18 +01:00
Alexis Engelke
9cdd35f82f
Decode VEX compact escapes more precisely
...
The single opcode byte follows the VEX prefix immediately.
2019-02-24 10:08:41 +01:00
Alexis Engelke
b2b29239b1
Disallow LOCK prefix for non-lockable instructions
2019-02-24 09:26:23 +01:00
Alexis Engelke
89d6b5a5a7
Refactor ModRM decoding
2019-02-24 09:25:19 +01:00
Alexis Engelke
1670a52047
Fix decoding of CVTTS[SD]2SI
2019-02-23 16:33:32 +01:00
Alexis Engelke
67ae0f8de8
Store 32-bit and 64-bit data in a single table
2019-02-23 16:33:01 +01:00
Alexis Engelke
256806e4b6
Use argparse
2019-02-23 15:26:04 +01:00
Alexis Engelke
da683d850a
Simplify storing of opcode to description mapping
2019-02-23 12:18:50 +01:00
Alexis Engelke
10e7a41972
Simplify handling of 32-bit and 64-bit encodings
2019-02-23 12:06:04 +01:00
Alexis Engelke
50ba38627b
Store instruction description as namedtuple
2019-02-23 11:53:25 +01:00
Alexis Engelke
3fbd0ff5b5
Deduplicate tables in addition to instructions
2019-02-23 11:09:24 +01:00
Alexis Engelke
ffa28357ce
Support tables with multiple roots
2019-02-23 11:04:57 +01:00
Alexis Engelke
81224d1748
Fix some FPU instruction operand sizes
2019-02-10 16:17:33 +01:00
Alexis Engelke
b328067e60
Minor update of instruction definitions
2019-02-10 10:49:22 +01:00
Alexis Engelke
dd86caa7f9
Fix RIP-relative address decoding
2019-02-03 20:31:49 +01:00
Alexis Engelke
e9878785da
Replace FD_OP with FD_OT to avoid macro collision
2019-02-03 20:31:27 +01:00
Alexis Engelke
3abf29d63e
Major rework of API and improved documentation
2019-01-23 20:03:40 +01:00
Alexis Engelke
a045588999
Remove some likeliness information
...
Much better information and performance can be achieved using PGO.
2019-01-22 13:47:37 +01:00
Alexis Engelke
20f6e8c073
Fix handling of 66h prefix on jumps
...
It turns out that in x86-64 mode, address and operand size overrides are
ignored by the processor. (Tested that on a real machine.)
Even libopcodes gets this wrong...
2019-01-14 19:53:46 +01:00
Alexis Engelke
a799024066
Specify address via parameter
...
This allows to decode instructions where the address of the buffer is
not the address of the instruction.
2019-01-14 19:52:03 +01:00
Alexis Engelke
55f6fda583
Add some test cases for prefix ordering
2019-01-13 20:39:57 +01:00
Alexis Engelke
8fdfe53822
Output more available information in formatter
...
The formatter now includes the following information:
- Segment overrides
- Address-size overrides
- REP/REPNZ prefixes
- LOCK prefix
- High-byte registers (determined using presence of REX prefix)
2019-01-13 20:38:15 +01:00
Alexis Engelke
2d1a9582b8
Handle prefix ordering correctly
2019-01-13 20:36:02 +01:00
Alexis Engelke
3ed7cb4a96
No longer expose PrefixSet in header
2019-01-13 18:43:46 +01:00
Alexis Engelke
9d3f34bcc6
No longer store sizes as bitfields
...
On most (x86) processors, using bitfields is low than using slightly
more memory.
2019-01-13 16:19:41 +01:00
Alexis Engelke
5bdafbbcf0
Fix VEX decoding with mandatory VEX.W bit
...
The Intel documentation is, well, inconsistent about this: at one point,
they say that the VEX.W prefix is ignored entirely in 32-bit mode, but
the instruction description indicates that a VEX.W can be required in
32-bit/compatibility mode as well.
2019-01-13 15:56:39 +01:00
Alexis Engelke
5532602000
Refactor prefix decoder
2019-01-13 15:54:47 +01:00
Alexis Engelke
4f4b2050c8
Allow prefix table at end of opcode
...
Some instructions, e.g. VZEROUPPER, have a prefix table but no
associated byte for that. Fix this by removing the prefix handling from
the table walking loop.
2019-01-13 15:53:48 +01:00
Alexis Engelke
d1110fae6a
Handle address size overrides
2019-01-13 14:27:04 +01:00
Alexis Engelke
80458e3288
Reduce space required by instruction width
2019-01-13 14:26:26 +01:00
Alexis Engelke
c05b555bb0
Remove non-existing function from header
2019-01-13 13:18:24 +01:00
Alexis Engelke
fbc37b9514
Annotate generated table with comments
2019-01-13 13:15:28 +01:00
Alexis Engelke
ed53b4a54d
Support 32 bit and 64 bit decoding with one binary
...
It is possible to configure the build process such that decoding of 32
bit and 64 bit instructions can be chosen at runtime using an additional
parameter of the decode function. The header file is now entirely
architecture-independent and no longer required any previous defines.
Decoding x86-64 still requires a 64-bit pointer size.
2019-01-13 11:58:59 +01:00
