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breaking! instrs: Decode VMOVS[SD] loads correctly

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These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
This commit is contained in:
Alexis Engelke
2021-01-10 12:12:26 +01:00
parent e86ea540b5
commit 96e513c8ea
2 changed files with 10 additions and 6 deletions
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12
instrs.txt
View File

@@ -860,14 +860,14 @@ VEX.66.L0.0f3adf RMI XMM XMM IMM8 - VAESKEYGENASSIST
# AVX # AVX
VEX.NP.0f10 RM XMM XMM - - VMOVUPS VEX.NP.0f10 RM XMM XMM - - VMOVUPS
VEX.66.0f10 RM XMM XMM - - VMOVUPD VEX.66.0f10 RM XMM XMM - - VMOVUPD
VEX.F3.LIG.0f10 RVM XMM XMM XMM32 - VMOVSS VEX.F3.LIG.0f10 RVM XMM128 XMM128 XMM32 - VMOVSS
VEX.F2.LIG.0f10 RVM XMM XMM XMM64 - VMOVSD VEX.F2.LIG.0f10 RVM XMM128 XMM128 XMM64 - VMOVSD
VEX.NP.0f11 MR XMM XMM - - VMOVUPS VEX.NP.0f11 MR XMM XMM - - VMOVUPS
VEX.66.0f11 MR XMM XMM - - VMOVUPD VEX.66.0f11 MR XMM XMM - - VMOVUPD
# TODO: VMOVSS/VMOVSD with memory operand have no VEX operand (and enforce V=0) VEX.F3.LIG.0f11/m MR XMM32 XMM32 - - VMOVSS
# Note that the dest operand size is incorrect in case of a reg-reg-reg encoding VEX.F3.LIG.0f11/r MVR XMM128 XMM128 XMM32 - VMOVSS
VEX.F3.LIG.0f11 MVR XMM32 XMM XMM32 - VMOVSS VEX.F2.LIG.0f11/m MR XMM64 XMM64 - - VMOVSD
VEX.F2.LIG.0f11 MVR XMM64 XMM XMM64 - VMOVSD VEX.F2.LIG.0f11/r MVR XMM128 XMM XMM64 - VMOVSD
VEX.NP.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPS VEX.NP.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPS
VEX.NP.L0.0f12/r RVM XMM XMM XMM - VMOVHLPS VEX.NP.L0.0f12/r RVM XMM XMM XMM - VMOVHLPS
VEX.66.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPD VEX.66.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPD

4
tests/test_decode.c
View File

@@ -330,6 +330,10 @@ main(int argc, char** argv)
TEST("\xc5\xf9\x6e\xc8", "vmovd xmm1, eax"); TEST("\xc5\xf9\x6e\xc8", "vmovd xmm1, eax");
TEST64("\xc4\xe1\xf9\x6e\xc8", "vmovq xmm1, rax"); TEST64("\xc4\xe1\xf9\x6e\xc8", "vmovq xmm1, rax");
TEST32("\xc4\xe1\xf9\x6e\xc8", "vmovd xmm1, eax"); TEST32("\xc4\xe1\xf9\x6e\xc8", "vmovd xmm1, eax");
TEST("\xc5\xf2\x10\xc2", "vmovss xmm0, xmm1, xmm2");
TEST("\xc5\xf6\x10\xc2", "vmovss xmm0, xmm1, xmm2"); // VEX.L=1
TEST("\xc5\xfa\x11\x04\x25\x34\x12\x00\x00", "vmovss dword ptr [0x1234], xmm0");
TEST("\xc5\xf2\x11\x04\x25\x34\x12\x00\x00", "UD"); // VEX.vvvv != 0
TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax");
TEST32("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); TEST32("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax");
TEST64("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, rax"); TEST64("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, rax");