From 96e513c8ea77011640abc906261288f383bd1415 Mon Sep 17 00:00:00 2001 From: Alexis Engelke Date: Sun, 10 Jan 2021 12:12:26 +0100 Subject: [PATCH] breaking! instrs: Decode VMOVS[SD] loads correctly These instruction ignore the VEX operand if the source operand is a memory location. API compatibility: separate handling for different operand types in the second and third operand (REG+REG vs. MEM+NONE) is needed. --- instrs.txt | 12 ++++++------ tests/test_decode.c | 4 ++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/instrs.txt b/instrs.txt index 52ac3b9..feb8a3b 100644 --- a/instrs.txt +++ b/instrs.txt @@ -860,14 +860,14 @@ VEX.66.L0.0f3adf RMI XMM XMM IMM8 - VAESKEYGENASSIST # AVX VEX.NP.0f10 RM XMM XMM - - VMOVUPS VEX.66.0f10 RM XMM XMM - - VMOVUPD -VEX.F3.LIG.0f10 RVM XMM XMM XMM32 - VMOVSS -VEX.F2.LIG.0f10 RVM XMM XMM XMM64 - VMOVSD +VEX.F3.LIG.0f10 RVM XMM128 XMM128 XMM32 - VMOVSS +VEX.F2.LIG.0f10 RVM XMM128 XMM128 XMM64 - VMOVSD VEX.NP.0f11 MR XMM XMM - - VMOVUPS VEX.66.0f11 MR XMM XMM - - VMOVUPD -# TODO: VMOVSS/VMOVSD with memory operand have no VEX operand (and enforce V=0) -# Note that the dest operand size is incorrect in case of a reg-reg-reg encoding -VEX.F3.LIG.0f11 MVR XMM32 XMM XMM32 - VMOVSS -VEX.F2.LIG.0f11 MVR XMM64 XMM XMM64 - VMOVSD +VEX.F3.LIG.0f11/m MR XMM32 XMM32 - - VMOVSS +VEX.F3.LIG.0f11/r MVR XMM128 XMM128 XMM32 - VMOVSS +VEX.F2.LIG.0f11/m MR XMM64 XMM64 - - VMOVSD +VEX.F2.LIG.0f11/r MVR XMM128 XMM XMM64 - VMOVSD VEX.NP.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPS VEX.NP.L0.0f12/r RVM XMM XMM XMM - VMOVHLPS VEX.66.L0.0f12/m RVM XMM XMM XMM64 - VMOVLPD diff --git a/tests/test_decode.c b/tests/test_decode.c index 9cb2f49..acc63ed 100644 --- a/tests/test_decode.c +++ b/tests/test_decode.c @@ -330,6 +330,10 @@ main(int argc, char** argv) TEST("\xc5\xf9\x6e\xc8", "vmovd xmm1, eax"); TEST64("\xc4\xe1\xf9\x6e\xc8", "vmovq xmm1, rax"); TEST32("\xc4\xe1\xf9\x6e\xc8", "vmovd xmm1, eax"); + TEST("\xc5\xf2\x10\xc2", "vmovss xmm0, xmm1, xmm2"); + TEST("\xc5\xf6\x10\xc2", "vmovss xmm0, xmm1, xmm2"); // VEX.L=1 + TEST("\xc5\xfa\x11\x04\x25\x34\x12\x00\x00", "vmovss dword ptr [0x1234], xmm0"); + TEST("\xc5\xf2\x11\x04\x25\x34\x12\x00\x00", "UD"); // VEX.vvvv != 0 TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); TEST32("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); TEST64("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, rax");