format: Format instructions with Intel syntax
This commit is contained in:
@@ -56,294 +56,384 @@ main(int argc, char** argv)
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int failed = 0;
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TEST("\x90", "[NOP]");
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TEST("\x90", "[NOP]");
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TEST32("\x2e\x90", "[cs:NOP]");
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TEST64("\x2e\x90", "[NOP]");
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TEST32("\x2e\x2e\x90", "[cs:NOP]");
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TEST64("\x2e\x2e\x90", "[NOP]");
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TEST32("\x2e\x26\x90", "[es:NOP]");
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TEST64("\x2e\x26\x90", "[NOP]");
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TEST32("\x26\x2e\x90", "[cs:NOP]");
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TEST64("\x26\x2e\x90", "[NOP]");
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TEST32("\x26\x65\x90", "[gs:NOP]");
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TEST64("\x26\x65\x90", "[gs:NOP]");
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TEST32("\x65\x26\x90", "[es:NOP]");
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TEST64("\x65\x26\x90", "[gs:NOP]");
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TEST("\x0f\x10\xc1", "[SSE_MOVUPS reg16:r0 reg16:r1]");
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TEST("\x66\x0f\x10\xc1", "[SSE_MOVUPD reg16:r0 reg16:r1]");
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TEST("\xf2\x66\x0f\x10\xc1", "[SSE_MOVSD reg16:r0 reg8:r1]");
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TEST("\xf3\x66\x0f\x10\xc1", "[SSE_MOVSS reg16:r0 reg4:r1]");
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TEST("\xf3\xf2\x66\x0f\x10\xc1", "[SSE_MOVSD reg16:r0 reg8:r1]");
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TEST("\xf2\x66\xf3\x66\x0f\x10\xc1", "[SSE_MOVSS reg16:r0 reg4:r1]");
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TEST64("\x48\x90", "[NOP]");
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TEST64("\x49\x90", "[XCHG reg8:r8 reg8:r0]");
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TEST64("\x48\x91", "[XCHG reg8:r1 reg8:r0]");
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TEST64("\x48\x26\x91", "[XCHG reg4:r1 reg4:r0]");
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TEST64("\x66\x90", "[NOP]");
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TEST("\x0f\xc7\x0f", "[CMPXCHGD_4 mem0:r7]");
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TEST64("\x48\x0f\xc7\x0f", "[CMPXCHGD_8 mem0:r7]");
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TEST("\x90", "nop");
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TEST("\xac", "lodsb");
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TEST32("\x2e\xac", "cs lodsb");
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TEST64("\x2e\xac", "lodsb");
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TEST32("\x2e\x2e\xac", "cs lodsb");
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TEST64("\x2e\x2e\xac", "lodsb");
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TEST32("\x2e\x26\xac", "es lodsb");
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TEST64("\x2e\x26\xac", "lodsb");
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TEST32("\x26\x2e\xac", "cs lodsb");
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TEST64("\x26\x2e\xac", "lodsb");
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TEST32("\x26\x65\xac", "gs lodsb");
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TEST64("\x26\x65\xac", "gs lodsb");
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TEST32("\x65\x26\xac", "es lodsb");
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TEST64("\x65\x26\xac", "gs lodsb");
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TEST("\x0f\x10\xc1", "movups xmm0, xmm1");
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TEST("\x66\x0f\x10\xc1", "movupd xmm0, xmm1");
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TEST("\xf2\x66\x0f\x10\xc1", "movsd xmm0, xmm1");
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TEST("\xf3\x66\x0f\x10\xc1", "movss xmm0, xmm1");
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TEST("\xf3\xf2\x66\x0f\x10\xc1", "movsd xmm0, xmm1");
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TEST("\xf2\x66\xf3\x66\x0f\x10\xc1", "movss xmm0, xmm1");
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TEST64("\x48\x90", "nop");
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TEST64("\x49\x90", "xchg r8, rax");
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TEST64("\x48\x91", "xchg rcx, rax");
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TEST64("\x48\x26\x91", "xchg ecx, eax");
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TEST64("\x66\x90", "nop");
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TEST32("\x0f\xc7\x0f", "cmpxchg8b qword ptr [edi]");
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TEST64("\x0f\xc7\x0f", "cmpxchg8b qword ptr [rdi]");
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TEST64("\x48\x0f\xc7\x0f", "cmpxchg16b xmmword ptr [rdi]");
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TEST("\x66", "PARTIAL");
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TEST("\x0f", "PARTIAL");
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TEST("\x0f\x38", "PARTIAL");
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TEST("\x0f\x3a", "PARTIAL");
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TEST("\x80", "PARTIAL");
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TEST("\x0F\x01\x22", "[SMSW mem2:r2]");
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TEST64("\x48\x0F\x01\x22", "[SMSW mem2:r2]");
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TEST("\x66\x0F\x01\x22", "[SMSW mem2:r2]");
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TEST("\x0F\x01\xE2", "[SMSW reg4:r2]");
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TEST("\x66\x0F\x01\xE2", "[SMSW reg2:r2]");
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TEST64("\x66\x48\x0F\x01\xE2", "[SMSW reg8:r2]");
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TEST32("\x66\x0f\x20\x00", "[MOV_CR reg4:r0 reg0:r0]"); // mod=0, 66h
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TEST64("\x66\x0f\x20\x00", "[MOV_CR reg8:r0 reg0:r0]"); // mod=0, 66h
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TEST32("\x0F\x01\x22", "smsw word ptr [edx]");
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TEST64("\x0F\x01\x22", "smsw word ptr [rdx]");
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TEST64("\x48\x0F\x01\x22", "smsw word ptr [rdx]");
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TEST32("\x66\x0F\x01\x22", "smsw word ptr [edx]");
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TEST64("\x66\x0F\x01\x22", "smsw word ptr [rdx]");
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TEST("\x0F\x01\xE2", "smsw edx");
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TEST("\x66\x0F\x01\xE2", "smsw dx");
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TEST64("\x66\x48\x0F\x01\xE2", "smsw rdx");
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TEST32("\x66\x0f\x20\x00", "mov eax, cr0"); // mod=0, 66h
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TEST64("\x66\x0f\x20\x00", "mov rax, cr0"); // mod=0, 66h
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TEST("\x0f\x20\xc8", "UD"); // cr1
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TEST32("\x0f\x20\xd0", "[MOV_CR reg4:r0 reg0:r2]"); // cr2
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TEST64("\x0f\x20\xd0", "[MOV_CR reg8:r0 reg0:r2]"); // cr2
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TEST64("\x48\x0f\x20\xd0", "[MOV_CR reg8:r0 reg0:r2]"); // cr2 + REX.W
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TEST32("\x0f\x20\xd0", "mov eax, cr2"); // cr2
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TEST64("\x0f\x20\xd0", "mov rax, cr2"); // cr2
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TEST64("\x48\x0f\x20\xd0", "mov rax, cr2"); // cr2 + REX.W
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TEST64("\x44\x0f\x20\x08", "UD"); // cr9
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TEST64("\x44\x0f\x21\x00", "UD"); // dr8
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TEST("\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
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TEST64("\x44\x8c\xc0", "[MOV_S2G reg2:r0 reg2:r0]");
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TEST("\x8c\xc0", "mov ax, es");
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TEST64("\x44\x8c\xc0", "mov ax, es");
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TEST64("\x44\x8c\xf0", "UD"); // no segment register 6
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TEST64("\x44\x8c\xf8", "UD"); // no segment register 7
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TEST("\x8e\xc0", "[MOV_G2S reg2:r0 reg2:r0]");
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TEST("\x8e\xc0", "mov es, ax");
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TEST("\x8e\xc8", "UD"); // No mov cs, eax
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TEST("\xd8\xc1", "[FADD reg0:r0 reg0:r1]");
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TEST("\xdc\xc1", "[FADD reg0:r1 reg0:r0]");
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TEST64("\x41\xd8\xc1", "[FADD reg0:r0 reg0:r1]"); // REX.B ignored
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TEST64("\xd9\xc9", "[FXCH reg0:r1]");
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TEST64("\xd9\xd0", "[FNOP]");
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TEST64("\x41\xdf\xe0", "[FSTSW reg2:r0]");
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TEST("\xd8\xc1", "fadd st(0), st(1)");
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TEST("\xdc\xc1", "fadd st(1), st(0)");
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TEST64("\x41\xd8\xc1", "fadd st(0), st(1)"); // REX.B ignored
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TEST64("\xd9\xc9", "fxch st(1)");
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TEST64("\xd9\xd0", "fnop");
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TEST64("\x41\xdf\xe0", "fstsw ax");
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// ModRM Test cases
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// reg
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TEST("\x01\xc0", "[ADD reg4:r0 reg4:r0]");
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TEST("\x01\xc1", "[ADD reg4:r1 reg4:r0]");
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TEST("\x01\xd0", "[ADD reg4:r0 reg4:r2]");
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TEST("\x01\xff", "[ADD reg4:r7 reg4:r7]");
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TEST64("\x41\x01\xd0", "[ADD reg4:r8 reg4:r2]");
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TEST64("\x45\x01\xd0", "[ADD reg4:r8 reg4:r10]");
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TEST64("\x45\x01\xff", "[ADD reg4:r15 reg4:r15]");
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TEST("\x01\xc0", "add eax, eax");
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TEST("\x01\xc1", "add ecx, eax");
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TEST("\x01\xd0", "add eax, edx");
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TEST("\x01\xff", "add edi, edi");
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TEST64("\x41\x01\xd0", "add r8d, edx");
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TEST64("\x45\x01\xd0", "add r8d, r10d");
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TEST64("\x45\x01\xff", "add r15d, r15d");
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// [reg]
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TEST("\x01\x00", "[ADD mem4:r0 reg4:r0]");
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TEST("\x01\x08", "[ADD mem4:r0 reg4:r1]");
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TEST("\x01\x01", "[ADD mem4:r1 reg4:r0]");
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TEST("\x01\x07", "[ADD mem4:r7 reg4:r0]");
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TEST("\x01\x38", "[ADD mem4:r0 reg4:r7]");
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TEST("\x01\x04\x24", "[ADD mem4:r4 reg4:r0]");
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TEST64("\x41\x01\x00", "[ADD mem4:r8 reg4:r0]");
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TEST64("\x44\x01\x08", "[ADD mem4:r0 reg4:r9]");
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TEST64("\x45\x01\x00", "[ADD mem4:r8 reg4:r8]");
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TEST64("\x41\x01\x07", "[ADD mem4:r15 reg4:r0]");
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TEST64("\x41\x01\x04\x24", "[ADD mem4:r12 reg4:r0]");
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TEST32("\x01\x00", "add dword ptr [eax], eax");
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TEST64("\x01\x00", "add dword ptr [rax], eax");
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TEST32("\x01\x08", "add dword ptr [eax], ecx");
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TEST64("\x01\x08", "add dword ptr [rax], ecx");
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TEST32("\x01\x01", "add dword ptr [ecx], eax");
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TEST64("\x01\x01", "add dword ptr [rcx], eax");
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TEST32("\x01\x07", "add dword ptr [edi], eax");
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TEST64("\x01\x07", "add dword ptr [rdi], eax");
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TEST32("\x01\x38", "add dword ptr [eax], edi");
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TEST64("\x01\x38", "add dword ptr [rax], edi");
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TEST32("\x01\x04\x24", "add dword ptr [esp], eax");
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TEST64("\x01\x04\x24", "add dword ptr [rsp], eax");
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TEST64("\x41\x01\x00", "add dword ptr [r8], eax");
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TEST64("\x44\x01\x08", "add dword ptr [rax], r9d");
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TEST64("\x45\x01\x00", "add dword ptr [r8], r8d");
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TEST64("\x41\x01\x07", "add dword ptr [r15], eax");
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TEST64("\x41\x01\x04\x24", "add dword ptr [r12], eax");
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// [disp32]
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TEST32("\x01\x05\x01\x00\x00\x00", "[ADD mem4:0x1 reg4:r0]");
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TEST32("\x01\x05\xff\xff\xff\xff", "[ADD mem4:-0x1 reg4:r0]");
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TEST("\x01\x04\x25\x01\x00\x00\x00", "[ADD mem4:0x1 reg4:r0]");
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TEST64("\x41\x01\x04\x25\x01\x00\x00\x00", "[ADD mem4:0x1 reg4:r0]");
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TEST32("\x01\x05\x01\x00\x00\x00", "add dword ptr [0x1], eax");
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TEST32("\x01\x05\xff\xff\xff\xff", "add dword ptr [0xffffffff], eax");
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TEST("\x01\x04\x25\x01\x00\x00\x00", "add dword ptr [0x1], eax");
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TEST32("\x01\x04\x25\x00\x00\x00\x80", "add dword ptr [0x80000000], eax");
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TEST64("\x01\x04\x25\x00\x00\x00\x80", "add dword ptr [0xffffffff80000000], eax");
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TEST64("\x41\x01\x04\x25\x01\x00\x00\x00", "add dword ptr [0x1], eax");
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// [rip+disp32]
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TEST64("\x01\x05\x01\x00\x00\x00", "[ADD mem4:r16+0x1 reg4:r0]");
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TEST64("\x41\x01\x05\x01\x00\x00\x00", "[ADD mem4:r16+0x1 reg4:r0]");
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TEST64("\x01\x05\x01\x00\x00\x00", "add dword ptr [rip+0x1], eax");
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TEST64("\x41\x01\x05\x01\x00\x00\x00", "add dword ptr [rip+0x1], eax");
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// [reg+disp32]
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TEST("\x01\x80\x01\x00\x00\x00", "[ADD mem4:r0+0x1 reg4:r0]");
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TEST32("\x01\x80\x01\x00\x00\x00", "add dword ptr [eax+0x1], eax");
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TEST64("\x01\x80\x01\x00\x00\x00", "add dword ptr [rax+0x1], eax");
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TEST32("\x01\x80\x00\x00\x00\x80", "add dword ptr [eax-0x80000000], eax");
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TEST64("\x01\x80\x00\x00\x00\x80", "add dword ptr [rax-0x80000000], eax");
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// [reg+eiz+disp32]
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TEST("\x01\x84\x25\x01\x00\x00\x00", "[ADD mem4:r5+0x1 reg4:r0]");
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TEST32("\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [ebp+0x1], eax");
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TEST64("\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [rbp+0x1], eax");
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// [reg+s*reg+disp32]
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TEST64("\x42\x01\x84\x25\x01\x00\x00\x00", "[ADD mem4:r5+1*r12+0x1 reg4:r0]");
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TEST64("\x42\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [rbp+1*r12+0x1], eax");
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TEST("\x04\x01", "[ADD reg1:r0 imm1:0x1]");
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TEST("\x66\x68\xff\xad", "[PUSH imm2:0xadff]");
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TEST32("\x68\xff\xad\x90\xbc", "[PUSH imm4:0xbc90adff]");
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TEST64("\x68\xff\xad\x90\xbc", "[PUSH imm8:0xffffffffbc90adff]");
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TEST("\x66\x6a\xff", "[PUSH imm2:0xffff]");
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TEST32("\x6a\xff", "[PUSH imm4:0xffffffff]");
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TEST64("\x6a\xff", "[PUSH imm8:0xffffffffffffffff]");
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TEST("\xb0\xf0", "[MOVABS reg1:r0 imm1:0xf0]");
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TEST("\xb8\xf0\xf0\xab\xff", "[MOVABS reg4:r0 imm4:0xffabf0f0]");
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TEST64("\x48\xb8\xf0\xf0\xab\xff\x00\x12\x12\xcd", "[MOVABS reg8:r0 imm8:0xcd121200ffabf0f0]");
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TEST64("\xcd\x80", "[INT imm1:0x80]");
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TEST("\x04\x01", "add al, 0x1");
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TEST("\x66\x68\xff\xad", "pushw 0xadff");
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TEST32("\x68\xff\xad\x90\xbc", "push 0xbc90adff");
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TEST64("\x68\xff\xad\x90\xbc", "push 0xffffffffbc90adff");
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TEST("\x66\x6a\xff", "pushw 0xffff");
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TEST32("\x6a\xff", "push 0xffffffff");
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TEST64("\x6a\xff", "push 0xffffffffffffffff");
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TEST("\xb0\xf0", "mov al, 0xf0");
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TEST("\x66\xb8\xf0\xf0", "mov ax, 0xf0f0");
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TEST("\xb8\xf0\xf0\xab\xff", "mov eax, 0xffabf0f0");
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TEST64("\x48\xb8\xf0\xf0\xab\xff\x00\x12\x12\xcd", "mov rax, 0xcd121200ffabf0f0");
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TEST64("\xcd\x80", "int 0x80");
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TEST("\x66\xc8\x00\x00\x00", "[ENTER_2 imm4:0x0]");
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TEST("\x66\xc8\x00\x0f\x00", "[ENTER_2 imm4:0xf00]");
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TEST("\x66\xc8\x00\x00\x01", "[ENTER_2 imm4:0x10000]");
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TEST32("\xc8\x00\x00\x00", "[ENTER_4 imm4:0x0]");
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TEST32("\xc8\x00\x0f\x00", "[ENTER_4 imm4:0xf00]");
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TEST32("\xc8\x00\x00\x01", "[ENTER_4 imm4:0x10000]");
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TEST64("\xc8\x00\x00\x00", "[ENTER_8 imm4:0x0]");
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TEST64("\xc8\x00\x0f\x00", "[ENTER_8 imm4:0xf00]");
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TEST64("\xc8\x00\x00\x01", "[ENTER_8 imm4:0x10000]");
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TEST("\x66\xc8\x00\x00\x00", "enterw 0x0, 0x0");
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TEST("\x66\xc8\x00\x0f\x00", "enterw 0xf00, 0x0");
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TEST("\x66\xc8\x00\x00\x01", "enterw 0x0, 0x1");
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TEST32("\xc8\x00\x00\x00", "enter 0x0, 0x0");
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TEST32("\xc8\x00\x0f\x00", "enter 0xf00, 0x0");
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TEST32("\xc8\x00\x00\x01", "enter 0x0, 0x1");
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TEST64("\xc8\x00\x00\x00", "enter 0x0, 0x0");
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TEST64("\xc8\x00\x0f\x00", "enter 0xf00, 0x0");
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TEST64("\xc8\x00\x00\x01", "enter 0x0, 0x1");
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TEST64("\xd3\xe0", "[SHL reg4:r0 reg1:r1]");
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TEST64("\x0f\xa5\xd0", "[SHLD reg4:r0 reg4:r2 reg1:r1]");
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TEST64("\xd3\xe0", "shl eax, cl");
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TEST64("\xd0\x3e", "sar byte ptr [rsi], 0x1");
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TEST64("\x0f\xa5\xd0", "shld eax, edx, cl");
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TEST("\x69\xC7\x08\x01\x00\x00", "[IMUL reg4:r0 reg4:r7 imm4:0x108]");
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TEST("\x6B\xC7\x08", "[IMUL reg4:r0 reg4:r7 imm4:0x8]");
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TEST("\x69\xC7\x08\x01\x00\x00", "imul eax, edi, 0x108");
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TEST("\x6B\xC7\x08", "imul eax, edi, 0x8");
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TEST("\x0f\x38\xf0\xd1", "UD"); // MOVBE doesn't allow register moves
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TEST("\x0f\x38\xf0\x11", "[MOVBE reg4:r2 mem4:r1]");
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TEST("\x66\x0f\x38\xf0\x11", "[MOVBE reg2:r2 mem2:r1]");
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TEST64("\x48\x0f\x38\xf0\x01", "[MOVBE reg8:r0 mem8:r1]");
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TEST("\xf2\x0f\x38\xf0\xd1", "[CRC32 reg4:r2 reg1:r1]");
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TEST("\xf2\x66\x0f\x38\xf1\xd1", "[CRC32 reg4:r2 reg2:r1]");
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TEST("\xf2\x0f\x38\xf1\xd1", "[CRC32 reg4:r2 reg4:r1]");
|
||||
TEST64("\xf2\x48\x0f\x38\xf1\xd1", "[CRC32 reg4:r2 reg8:r1]");
|
||||
TEST64("\xf2\x4c\x0f\x38\xf1\xd1", "[CRC32 reg4:r10 reg8:r1]");
|
||||
TEST32("\x0f\x38\xf0\x11", "movbe edx, dword ptr [ecx]");
|
||||
TEST64("\x0f\x38\xf0\x11", "movbe edx, dword ptr [rcx]");
|
||||
TEST32("\x66\x0f\x38\xf0\x11", "movbe dx, word ptr [ecx]");
|
||||
TEST64("\x66\x0f\x38\xf0\x11", "movbe dx, word ptr [rcx]");
|
||||
TEST64("\x48\x0f\x38\xf0\x01", "movbe rax, qword ptr [rcx]");
|
||||
TEST("\xf2\x0f\x38\xf0\xd1", "crc32 edx, cl");
|
||||
TEST("\xf2\x66\x0f\x38\xf1\xd1", "crc32 edx, cx");
|
||||
TEST("\xf2\x0f\x38\xf1\xd1", "crc32 edx, ecx");
|
||||
TEST64("\xf2\x48\x0f\x38\xf1\xd1", "crc32 edx, rcx");
|
||||
TEST64("\xf2\x4c\x0f\x38\xf1\xd1", "crc32 r10d, rcx");
|
||||
|
||||
TEST("\x8d\x00", "[LEA reg4:r0 mem0:r0]");
|
||||
TEST32("\x8d\x00", "lea eax, [eax]");
|
||||
TEST64("\x8d\x00", "lea eax, [rax]");
|
||||
TEST("\x8d\xc0", "UD");
|
||||
|
||||
TEST32("\x40", "[INC reg4:r0]");
|
||||
TEST32("\x43", "[INC reg4:r3]");
|
||||
TEST32("\x66\x47", "[INC reg2:r7]");
|
||||
TEST("\xfe\xc0", "[INC reg1:r0]");
|
||||
TEST("\xfe\xc4", "[INC reg1:r0h]");
|
||||
TEST("\xff\xc0", "[INC reg4:r0]");
|
||||
TEST("\xff\xc4", "[INC reg4:r4]");
|
||||
TEST("\xff\x00", "[INC mem4:r0]");
|
||||
TEST("\xf0\xff\x00", "[lock:INC mem4:r0]");
|
||||
TEST("\x66\xff\xc0", "[INC reg2:r0]");
|
||||
TEST("\x66\xff\xc4", "[INC reg2:r4]");
|
||||
TEST64("\x48\xff\xc0", "[INC reg8:r0]");
|
||||
TEST64("\x48\xff\xc4", "[INC reg8:r4]");
|
||||
TEST64("\x49\xff\xc7", "[INC reg8:r15]");
|
||||
TEST32("\x40", "inc eax");
|
||||
TEST32("\x43", "inc ebx");
|
||||
TEST32("\x66\x47", "inc di");
|
||||
TEST("\xfe\xc0", "inc al");
|
||||
TEST("\xfe\xc4", "inc ah");
|
||||
TEST("\xff\xc0", "inc eax");
|
||||
TEST("\xff\xc4", "inc esp");
|
||||
TEST32("\xff\x00", "inc dword ptr [eax]");
|
||||
TEST64("\xff\x00", "inc dword ptr [rax]");
|
||||
TEST32("\xf0\xff\x00", "lock inc dword ptr [eax]");
|
||||
TEST64("\xf0\xff\x00", "lock inc dword ptr [rax]");
|
||||
TEST("\x66\xff\xc0", "inc ax");
|
||||
TEST("\x66\xff\xc4", "inc sp");
|
||||
TEST64("\x48\xff\xc0", "inc rax");
|
||||
TEST64("\x48\xff\xc4", "inc rsp");
|
||||
TEST64("\x49\xff\xc7", "inc r15");
|
||||
|
||||
TEST32("\xe9\x00\x00\x00\x00", "[JMP off4:eip+0x0]");
|
||||
TEST32("\x66\xe9\x01\x00", "[JMP off2:ip+0x1]");
|
||||
TEST64("\xe9\x00\x00\x00\x00", "[JMP off8:rip+0x0]");
|
||||
TEST64("\x66\xe9\x00\x00\x00\x00", "[JMP off8:rip+0x0]");
|
||||
TEST64("\x66\xeb\x00", "[JMP off8:rip+0x0]");
|
||||
TEST64("\x66\xeb\xff", "[JMP off8:rip+0xffffffffffffffff]");
|
||||
TEST32("\xe9\x00\x00\x00\x00", "jmp 0x5");
|
||||
TEST32("\x66\xe9\x01\x00", "jmpw 0x5");
|
||||
TEST64("\xe9\x00\x00\x00\x00", "jmp 0x5");
|
||||
TEST64("\x66\xe9\x00\x00\x00\x00", "jmp 0x6");
|
||||
TEST64("\x66\xeb\x00", "jmp 0x3");
|
||||
TEST64("\x66\xeb\xff", "jmp 0x2");
|
||||
TEST("\x66\xe9\x00", "PARTIAL");
|
||||
TEST("\x66\xe9", "PARTIAL");
|
||||
TEST32("\xc7\xf8\xd3\x9c\xff\xff", "[XBEGIN off4:eip+0xffff9cd3]");
|
||||
TEST32("\x66\xc7\xf8\xd3\x9c", "[XBEGIN off4:eip+0xffff9cd3]");
|
||||
TEST64("\xc7\xf8\xd3\x9c\xff\xff", "[XBEGIN off8:rip+0xffffffffffff9cd3]");
|
||||
TEST64("\x66\xc7\xf8\xd3\x9c", "[XBEGIN off8:rip+0xffffffffffff9cd3]");
|
||||
TEST32("\xc7\xf8\xd3\x9c\xff\xff", "xbegin 0xffff9cd9");
|
||||
TEST32("\x66\xc7\xf8\xd3\x9c", "xbegin 0xffff9cd8");
|
||||
TEST64("\xc7\xf8\xd3\x9c\xff\xff", "xbegin 0xffffffffffff9cd9");
|
||||
TEST64("\x66\xc7\xf8\xd3\x9c", "xbegin 0xffffffffffff9cd8");
|
||||
|
||||
|
||||
TEST("\xa5", "[MOVS_4]");
|
||||
TEST("\x66\xa5", "[MOVS_2]");
|
||||
TEST("\xf3\xa5", "[rep:MOVS_4]");
|
||||
TEST("\xf3\x66\xa5", "[rep:MOVS_2]");
|
||||
TEST("\xa5", "movsd");
|
||||
TEST("\x66\xa5", "movsw");
|
||||
TEST("\xf3\xa5", "rep movsd");
|
||||
TEST("\xf3\x66\xa5", "rep movsw");
|
||||
|
||||
TEST("\x66\x0f\xbe\xc2", "[MOVSX reg2:r0 reg1:r2]");
|
||||
TEST("\x0f\xbe\xc2", "[MOVSX reg4:r0 reg1:r2]");
|
||||
TEST("\x0f\xbf\xc2", "[MOVSX reg4:r0 reg2:r2]");
|
||||
TEST64("\x48\x0f\xbf\xc2", "[MOVSX reg8:r0 reg2:r2]");
|
||||
TEST64("\x48\x63\xc2", "[MOVSX reg8:r0 reg4:r2]");
|
||||
TEST("\x66\x0f\xbe\xc2", "movsx ax, dl");
|
||||
TEST("\x0f\xbe\xc2", "movsx eax, dl");
|
||||
TEST("\x0f\xbf\xc2", "movsx eax, dx");
|
||||
TEST64("\x48\x0f\xbf\xc2", "movsx rax, dx");
|
||||
TEST64("\x48\x63\xc2", "movsx rax, edx");
|
||||
|
||||
TEST32("\x66\xc3", "[RET_2]");
|
||||
TEST32("\x66\xc2\x00\x00", "[RET_2 imm2:0x0]");
|
||||
TEST32("\x66\xc2\x0d\x00", "[RET_2 imm2:0xd]");
|
||||
TEST32("\x66\xc2\x0d\xff", "[RET_2 imm2:0xff0d]");
|
||||
TEST64("\x66\xc3", "[RET_8]");
|
||||
TEST64("\x66\xc2\x00\x00", "[RET_8 imm2:0x0]");
|
||||
TEST64("\x66\xc2\x0d\x00", "[RET_8 imm2:0xd]");
|
||||
TEST64("\x66\xc2\x0d\xff", "[RET_8 imm2:0xff0d]");
|
||||
TEST32("\xc3", "[RET_4]");
|
||||
TEST32("\xc2\x00\x00", "[RET_4 imm2:0x0]");
|
||||
TEST32("\xc2\x0d\x00", "[RET_4 imm2:0xd]");
|
||||
TEST32("\xc2\x0d\xff", "[RET_4 imm2:0xff0d]");
|
||||
TEST64("\xc3", "[RET_8]");
|
||||
TEST64("\xc2\x00\x00", "[RET_8 imm2:0x0]");
|
||||
TEST64("\xc2\x0d\x00", "[RET_8 imm2:0xd]");
|
||||
TEST64("\xc2\x0d\xff", "[RET_8 imm2:0xff0d]");
|
||||
TEST32("\x66\xc3", "retw");
|
||||
TEST32("\x66\xc2\x00\x00", "retw 0x0");
|
||||
TEST32("\x66\xc2\x0d\x00", "retw 0xd");
|
||||
TEST32("\x66\xc2\x0d\xff", "retw 0xff0d");
|
||||
TEST64("\x66\xc3", "ret");
|
||||
TEST64("\x66\xc2\x00\x00", "ret 0x0");
|
||||
TEST64("\x66\xc2\x0d\x00", "ret 0xd");
|
||||
TEST64("\x66\xc2\x0d\xff", "ret 0xff0d");
|
||||
TEST32("\xc3", "ret");
|
||||
TEST32("\xc2\x00\x00", "ret 0x0");
|
||||
TEST32("\xc2\x0d\x00", "ret 0xd");
|
||||
TEST32("\xc2\x0d\xff", "ret 0xff0d");
|
||||
TEST64("\xc3", "ret");
|
||||
TEST64("\xc2\x00\x00", "ret 0x0");
|
||||
TEST64("\xc2\x0d\x00", "ret 0xd");
|
||||
TEST64("\xc2\x0d\xff", "ret 0xff0d");
|
||||
|
||||
// NFx/66+F2/F3 combinations
|
||||
TEST("\x0f\xc7\xf0", "[RDRAND reg4:r0]");
|
||||
TEST64("\x48\x0f\xc7\xf0", "[RDRAND reg8:r0]");
|
||||
TEST("\x66\x0f\xc7\xf0", "[RDRAND reg2:r0]");
|
||||
TEST64("\x66\x48\x0f\xc7\xf0", "[RDRAND reg8:r0]");
|
||||
TEST("\x0f\xc7\xf8", "[RDSEED reg4:r0]");
|
||||
TEST64("\x48\x0f\xc7\xf8", "[RDSEED reg8:r0]");
|
||||
TEST("\x66\x0f\xc7\xf8", "[RDSEED reg2:r0]");
|
||||
TEST64("\x66\x48\x0f\xc7\xf8", "[RDSEED reg8:r0]");
|
||||
TEST32("\xf3\x0f\xc7\xf8", "[RDPID reg4:r0]");
|
||||
TEST32("\x66\xf3\x0f\xc7\xf8", "[RDPID reg4:r0]");
|
||||
TEST32("\xf3\x66\x0f\xc7\xf8", "[RDPID reg4:r0]");
|
||||
TEST64("\xf3\x0f\xc7\xf8", "[RDPID reg8:r0]");
|
||||
TEST64("\x66\xf3\x0f\xc7\xf8", "[RDPID reg8:r0]");
|
||||
TEST64("\xf3\x66\x0f\xc7\xf8", "[RDPID reg8:r0]");
|
||||
TEST("\x0f\xc7\xf0", "rdrand eax");
|
||||
TEST64("\x48\x0f\xc7\xf0", "rdrand rax");
|
||||
TEST("\x66\x0f\xc7\xf0", "rdrand ax");
|
||||
TEST64("\x66\x48\x0f\xc7\xf0", "rdrand rax");
|
||||
TEST("\x0f\xc7\xf8", "rdseed eax");
|
||||
TEST64("\x48\x0f\xc7\xf8", "rdseed rax");
|
||||
TEST("\x66\x0f\xc7\xf8", "rdseed ax");
|
||||
TEST64("\x66\x48\x0f\xc7\xf8", "rdseed rax");
|
||||
TEST32("\xf3\x0f\xc7\xf8", "rdpid eax");
|
||||
TEST32("\x66\xf3\x0f\xc7\xf8", "rdpid eax");
|
||||
TEST32("\xf3\x66\x0f\xc7\xf8", "rdpid eax");
|
||||
TEST64("\xf3\x0f\xc7\xf8", "rdpid rax");
|
||||
TEST64("\x66\xf3\x0f\xc7\xf8", "rdpid rax");
|
||||
TEST64("\xf3\x66\x0f\xc7\xf8", "rdpid rax");
|
||||
TEST64("\xf3\x0f\xc7\x00", "UD");
|
||||
TEST64("\x0f\xc7\x30", "[VMPTRLD mem8:r0]");
|
||||
TEST64("\x66\x0f\xc7\x30", "[VMCLEAR mem8:r0]");
|
||||
TEST64("\xf3\x0f\xc7\x30", "[VMXON mem8:r0]");
|
||||
TEST64("\x0f\xc7\x30", "vmptrld qword ptr [rax]");
|
||||
TEST64("\x66\x0f\xc7\x30", "vmclear qword ptr [rax]");
|
||||
TEST64("\xf3\x0f\xc7\x30", "vmxon qword ptr [rax]");
|
||||
|
||||
TEST64("\x0f\x09", "[WBINVD]");
|
||||
TEST64("\xf3\x0f\x09", "[WBNOINVD]");
|
||||
TEST64("\x0f\x09", "wbinvd");
|
||||
TEST64("\xf3\x0f\x09", "wbnoinvd");
|
||||
|
||||
TEST64("\x0f\xae\xe8", "[LFENCE]");
|
||||
TEST64("\x0f\xae\xe8", "lfence");
|
||||
|
||||
TEST("\xf3\x0f\x2a\xc1", "[SSE_CVTSI2SS reg4:r0 reg4:r1]");
|
||||
TEST("\xf3\x66\x0f\x2a\xc1", "[SSE_CVTSI2SS reg4:r0 reg4:r1]");
|
||||
TEST("\x66\xf3\x0f\x2a\xc1", "[SSE_CVTSI2SS reg4:r0 reg4:r1]");
|
||||
TEST64("\xf3\x48\x0f\x2a\xc1", "[SSE_CVTSI2SS reg4:r0 reg8:r1]");
|
||||
TEST64("\x66\xf3\x48\x0f\x2a\xc1", "[SSE_CVTSI2SS reg4:r0 reg8:r1]");
|
||||
TEST64("\x66\x0f\x50\xc1", "[SSE_MOVMSKPD reg8:r0 reg16:r1]");
|
||||
TEST("\x66\x0f\xc6\xc0\x01", "[SSE_SHUFPD reg16:r0 reg16:r0 imm1:0x1]");
|
||||
TEST("\x66\x0f\x71\xd0\x01", "[SSE_PSRLW reg16:r0 imm1:0x1]");
|
||||
TEST("\x66\x0f\x3a\x20\xc4\x01", "[SSE_PINSRB reg16:r0 reg1:r4 imm1:0x1]");
|
||||
TEST("\xf3\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx");
|
||||
TEST("\xf3\x66\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx");
|
||||
TEST("\x66\xf3\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx");
|
||||
TEST64("\xf3\x48\x0f\x2a\xc1", "cvtsi2ss xmm0, rcx");
|
||||
TEST64("\x66\xf3\x48\x0f\x2a\xc1", "cvtsi2ss xmm0, rcx");
|
||||
TEST64("\x66\x0f\x50\xc1", "movmskpd rax, xmm1");
|
||||
TEST("\x66\x0f\xc6\xc0\x01", "shufpd xmm0, xmm0, 0x1");
|
||||
TEST("\x66\x0f\x71\xd0\x01", "psrlw xmm0, 0x1");
|
||||
TEST("\x66\x0f\x3a\x20\xc4\x01", "pinsrb xmm0, spl, 0x1");
|
||||
TEST("\x66\x0f\x71\x10\x01", "UD");
|
||||
|
||||
TEST32("\xc4\x00", "[LES reg4:r0 mem0:r0]");
|
||||
TEST32("\xc5\x00", "[LDS reg4:r0 mem0:r0]");
|
||||
TEST("\xc5\xf2\x2a\xc0", "[VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]");
|
||||
TEST32("\xc4\x00", "les eax, fword ptr [eax]");
|
||||
TEST32("\xc5\x00", "lds eax, fword ptr [eax]");
|
||||
TEST32("\x0f\xb2\x00", "lss eax, fword ptr [eax]");
|
||||
TEST64("\x0f\xb2\x00", "lss eax, fword ptr [rax]");
|
||||
TEST64("\x48\x0f\xb2\x00", "lss rax, fword ptr [rax]");
|
||||
TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax");
|
||||
TEST("\xf3\xc5\xf2\x2a\xc0", "UD"); // VEX+REP
|
||||
TEST("\xf2\xc5\xf2\x2a\xc0", "UD"); // VEX+REPNZ
|
||||
TEST("\xf2\xf3\xc5\xf2\x2a\xc0", "UD"); // VEX+REP+REPNZ
|
||||
TEST("\x66\xc5\xf2\x2a\xc0", "UD"); // VEX+66
|
||||
TEST("\xf0\xc5\xf2\x2a\xc0", "UD"); // VEX+LOCK
|
||||
TEST64("\x40\xc5\xf2\x2a\xc0", "UD"); // VEX+REX
|
||||
TEST64("\x40\x26\xc5\xf2\x2a\xc0", "[VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]"); // VEX+REX, but REX doesn't precede VEX
|
||||
TEST64("\x40\x26\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); // VEX+REX, but REX doesn't precede VEX
|
||||
|
||||
TEST("\xf3\x0f\x7e\x5c\x24\x08", "[SSE_MOVQ reg16:r3 mem8:r4+0x8]");
|
||||
TEST32("\xc4\xe1\x00\x58\xc1", "[VADDPS reg16:r0 reg16:r7 reg16:r1]"); // MSB in vvvv ignored
|
||||
TEST64("\xc4\xe1\x00\x58\xc1", "[VADDPS reg16:r0 reg16:r15 reg16:r1]");
|
||||
TEST32("\xc4\xc1\x78\x58\xc0", "[VADDPS reg16:r0 reg16:r0 reg16:r0]"); // VEX.B ignored in 32-bit
|
||||
TEST64("\xc4\xc1\x78\x58\xc0", "[VADDPS reg16:r0 reg16:r0 reg16:r8]");
|
||||
TEST("\xc5\xf9\x6e\xc8", "[VMOVD reg4:r1 reg4:r0]");
|
||||
TEST64("\xc4\xe1\xf9\x6e\xc8", "[VMOVQ reg8:r1 reg8:r0]");
|
||||
TEST32("\xc4\xe1\xf9\x6e\xc8", "[VMOVD reg4:r1 reg4:r0]");
|
||||
TEST("\xc5\xf2\x2a\xc0", "[VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]");
|
||||
TEST32("\xc4\xe1\xf2\x2a\xc0", "[VCVTSI2SS reg16:r0 reg16:r1 reg4:r0]");
|
||||
TEST64("\xc4\xe1\xf2\x2a\xc0", "[VCVTSI2SS reg16:r0 reg16:r1 reg8:r0]");
|
||||
TEST64("\xc4\xe2\x75\x90\x04\xe7", "[VPGATHERDD reg32:r0 mem32:r7+8*r4 reg32:r1]");
|
||||
TEST32("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [esp+0x8]");
|
||||
TEST64("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [rsp+0x8]");
|
||||
TEST32("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm7, xmm1"); // MSB in vvvv ignored
|
||||
TEST64("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm15, xmm1");
|
||||
TEST32("\xc4\xc1\x78\x58\xc0", "vaddps xmm0, xmm0, xmm0"); // VEX.B ignored in 32-bit
|
||||
TEST64("\xc4\xc1\x78\x58\xc0", "vaddps xmm0, xmm0, xmm8");
|
||||
TEST("\xc5\xf9\x6e\xc8", "vmovd xmm1, eax");
|
||||
TEST64("\xc4\xe1\xf9\x6e\xc8", "vmovq xmm1, rax");
|
||||
TEST32("\xc4\xe1\xf9\x6e\xc8", "vmovd xmm1, eax");
|
||||
TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax");
|
||||
TEST32("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax");
|
||||
TEST64("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, rax");
|
||||
TEST64("\xc4\xe2\x75\x90\x04\xe7", "vpgatherdd ymm0, ymmword ptr [rdi+8*rsp], ymm1");
|
||||
|
||||
TEST("\xc4\xe3\x79\x14\xc0\x00", "[VPEXTRB reg1:r0 reg16:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\xf9\x14\xc0\x00", "[VPEXTRB reg1:r0 reg16:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\x79\x15\xc0\x00", "[VPEXTRW reg2:r0 reg16:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\xf9\x15\xc0\x00", "[VPEXTRW reg2:r0 reg16:r0 imm1:0x0]");
|
||||
TEST32("\xc4\xe1\x79\xc5\xc0\x00", "[VPEXTRW reg4:r0 reg16:r0 imm1:0x0]");
|
||||
TEST64("\xc4\xe1\x79\xc5\xc0\x00", "[VPEXTRW reg8:r0 reg16:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\x79\x16\xc0\x00", "[VPEXTRD reg4:r0 reg16:r0 imm1:0x0]");
|
||||
TEST32("\xc4\xe3\xf9\x16\xc0\x00", "[VPEXTRD reg4:r0 reg16:r0 imm1:0x0]");
|
||||
TEST64("\xc4\xe3\xf9\x16\xc0\x00", "[VPEXTRQ reg8:r0 reg16:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\x79\x14\xc0\x00", "vpextrb al, xmm0, 0x0");
|
||||
TEST("\xc4\xe3\xf9\x14\xc0\x00", "vpextrb al, xmm0, 0x0");
|
||||
TEST("\xc4\xe3\x79\x15\xc0\x00", "vpextrw ax, xmm0, 0x0");
|
||||
TEST("\xc4\xe3\xf9\x15\xc0\x00", "vpextrw ax, xmm0, 0x0");
|
||||
TEST32("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw eax, xmm0, 0x0");
|
||||
TEST64("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw rax, xmm0, 0x0");
|
||||
TEST("\xc4\xe3\x79\x16\xc0\x00", "vpextrd eax, xmm0, 0x0");
|
||||
TEST32("\xc4\xe3\xf9\x16\xc0\x00", "vpextrd eax, xmm0, 0x0");
|
||||
TEST64("\xc4\xe3\xf9\x16\xc0\x00", "vpextrq rax, xmm0, 0x0");
|
||||
|
||||
TEST("\xc4\xe3\x71\x20\xc0\x00", "[VPINSRB reg16:r0 reg16:r1 reg1:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\xf1\x20\xc0\x00", "[VPINSRB reg16:r0 reg16:r1 reg1:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe1\x71\xc4\xc0\x00", "[VPINSRW reg16:r0 reg16:r1 reg2:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe1\xf1\xc4\xc0\x00", "[VPINSRW reg16:r0 reg16:r1 reg2:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\x71\x22\xc0\x00", "[VPINSRD reg16:r0 reg16:r1 reg4:r0 imm1:0x0]");
|
||||
TEST32("\xc4\xe3\xf1\x22\xc0\x00", "[VPINSRD reg16:r0 reg16:r1 reg4:r0 imm1:0x0]");
|
||||
TEST64("\xc4\xe3\xf1\x22\xc0\x00", "[VPINSRQ reg16:r0 reg16:r1 reg8:r0 imm1:0x0]");
|
||||
TEST("\xc4\xe3\x71\x20\xc0\x00", "vpinsrb xmm0, xmm1, al, 0x0");
|
||||
TEST("\xc4\xe3\xf1\x20\xc0\x00", "vpinsrb xmm0, xmm1, al, 0x0");
|
||||
TEST("\xc4\xe1\x71\xc4\xc0\x00", "vpinsrw xmm0, xmm1, ax, 0x0");
|
||||
TEST("\xc4\xe1\xf1\xc4\xc0\x00", "vpinsrw xmm0, xmm1, ax, 0x0");
|
||||
TEST("\xc4\xe3\x71\x22\xc0\x00", "vpinsrd xmm0, xmm1, eax, 0x0");
|
||||
TEST32("\xc4\xe3\xf1\x22\xc0\x00", "vpinsrd xmm0, xmm1, eax, 0x0");
|
||||
TEST64("\xc4\xe3\xf1\x22\xc0\x00", "vpinsrq xmm0, xmm1, rax, 0x0");
|
||||
TEST("\xc4\xe3\x75\x20\xc0\x00", "UD"); // VEX.L != 0
|
||||
TEST("\xc4\xe1\x75\xc4\xc0\x00", "UD"); // VEX.L != 0
|
||||
TEST("\xc4\xe1\xf5\xc4\xc0\x00", "UD"); // VEX.L != 0
|
||||
TEST("\xc4\xe3\x75\x22\xc0\x00", "UD"); // VEX.L != 0
|
||||
TEST("\xc4\xe3\xf5\x22\xc0\x00", "UD"); // VEX.L != 0
|
||||
|
||||
TEST("\xc4\xe2\x71\x45\xc2", "[VPSRLVD reg16:r0 reg16:r1 reg16:r2]");
|
||||
TEST("\xc4\xe2\x75\x45\xc2", "[VPSRLVD reg32:r0 reg32:r1 reg32:r2]");
|
||||
TEST("\xc4\xe2\xf1\x45\xc2", "[VPSRLVQ reg16:r0 reg16:r1 reg16:r2]");
|
||||
TEST("\xc4\xe2\xf5\x45\xc2", "[VPSRLVQ reg32:r0 reg32:r1 reg32:r2]");
|
||||
TEST("\xc4\xe2\x71\x45\xc2", "vpsrlvd xmm0, xmm1, xmm2");
|
||||
TEST("\xc4\xe2\x75\x45\xc2", "vpsrlvd ymm0, ymm1, ymm2");
|
||||
TEST("\xc4\xe2\xf1\x45\xc2", "vpsrlvq xmm0, xmm1, xmm2");
|
||||
TEST("\xc4\xe2\xf5\x45\xc2", "vpsrlvq ymm0, ymm1, ymm2");
|
||||
|
||||
TEST("\xc4\xe2\x7d\x5a\x20", "[VBROADCASTI128 reg32:r4 mem16:r0]");
|
||||
TEST64("\xc4\x62\x7d\x5a\x20", "[VBROADCASTI128 reg32:r12 mem16:r0]");
|
||||
TEST32("\xc4\xe2\x7d\x5a\x20", "vbroadcasti128 ymm4, xmmword ptr [eax]");
|
||||
TEST64("\xc4\xe2\x7d\x5a\x20", "vbroadcasti128 ymm4, xmmword ptr [rax]");
|
||||
TEST64("\xc4\x62\x7d\x5a\x20", "vbroadcasti128 ymm12, xmmword ptr [rax]");
|
||||
TEST("\xc4\xe2\x75\x5a\x20", "UD"); // VEX.vvvv != 1111
|
||||
TEST("\xc4\xe2\x7d\x5a\xc0", "UD"); // ModRM.mod != 11
|
||||
TEST("\xc4\xe2\x79\x5a\x20", "UD"); // VEX.L != 1
|
||||
TEST("\xc4\xe2\xfd\x5a\x20", "UD"); // VEX.W != 0
|
||||
|
||||
// Intel-Syntax special cases
|
||||
TEST("\x66\x98", "cbw");
|
||||
TEST("\x98", "cwde");
|
||||
TEST64("\x48\x98", "cdqe");
|
||||
TEST("\x66\x99", "cwd");
|
||||
TEST("\x99", "cdq");
|
||||
TEST64("\x48\x99", "cqo");
|
||||
|
||||
TEST32("\x0f\xae\x00", "fxsave [eax]");
|
||||
TEST64("\x0f\xae\x00", "fxsave [rax]");
|
||||
TEST64("\x48\x0f\xae\x00", "fxsave64 [rax]");
|
||||
TEST32("\x66\xff\xe0", "jmp ax");
|
||||
TEST64("\x66\xff\xe0", "jmp rax");
|
||||
TEST32("\x66\x70\x00", "jow 0x3");
|
||||
TEST64("\x66\x70\x00", "jo 0x3");
|
||||
TEST32("\xe3\xfe", "jecxz 0x0");
|
||||
TEST64("\xe3\xfe", "jrcxz 0x0");
|
||||
TEST32("\x67\xe3\xfd", "jcxz 0x0");
|
||||
TEST64("\x67\xe3\xfd", "jecxz 0x0");
|
||||
TEST("\xa5", "movsd");
|
||||
TEST("\x64\xa5", "fs movsd");
|
||||
TEST32("\x2e\xa5", "cs movsd");
|
||||
TEST64("\x2e\xa5", "movsd");
|
||||
TEST32("\x67\xa5", "addr16 movsd");
|
||||
TEST64("\x67\xa5", "addr32 movsd");
|
||||
TEST("\xaf", "scasd");
|
||||
TEST("\x64\xaf", "scasd"); // SCAS doesn't use segment overrides
|
||||
TEST("\xec", "inb");
|
||||
TEST32("\x66\x61", "popaw");
|
||||
TEST32("\x61", "popad");
|
||||
TEST("\x66\x9d", "popfw");
|
||||
TEST32("\x9d", "popfd");
|
||||
TEST64("\x9d", "popfq");
|
||||
TEST("\x66\xcf", "iretw");
|
||||
TEST("\xcf", "iretd");
|
||||
TEST64("\x48\xcf", "iretq");
|
||||
TEST32("\x06", "push es");
|
||||
TEST32("\x66\x06", "pushw es");
|
||||
TEST32("\x07", "pop es");
|
||||
TEST32("\x66\x07", "popw es");
|
||||
TEST32("\x0e", "push cs");
|
||||
TEST32("\x66\x0e", "pushw cs");
|
||||
TEST32("\x16", "push ss");
|
||||
TEST32("\x66\x16", "pushw ss");
|
||||
TEST32("\x17", "pop ss");
|
||||
TEST32("\x66\x17", "popw ss");
|
||||
TEST("\x0f\xa8", "push gs");
|
||||
TEST("\x66\x0f\xa8", "pushw gs");
|
||||
TEST("\x0f\xa9", "pop gs");
|
||||
TEST("\x66\x0f\xa9", "popw gs");
|
||||
TEST32("\x0f\x21\xd0", "mov eax, dr2");
|
||||
TEST64("\x0f\x21\xd0", "mov rax, dr2");
|
||||
TEST32("\x62\x00", "bound eax, qword ptr [eax]");
|
||||
TEST32("\x66\x62\x00", "bound ax, dword ptr [eax]");
|
||||
TEST32("\x0f\xae\x38", "clflush byte ptr [eax]");
|
||||
TEST64("\x0f\xae\x38", "clflush byte ptr [rax]");
|
||||
TEST32("\xdd\x00", "fld qword ptr [eax]");
|
||||
TEST64("\xdd\x00", "fld qword ptr [rax]");
|
||||
TEST32("\xdb\x28", "fld tbyte ptr [eax]");
|
||||
TEST64("\xdb\x28", "fld tbyte ptr [rax]");
|
||||
TEST32("\xd9\x20", "fldenv [eax]");
|
||||
TEST64("\xd9\x20", "fldenv [rax]");
|
||||
|
||||
puts(failed ? "Some tests FAILED" : "All tests PASSED");
|
||||
return failed ? EXIT_FAILURE : EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user