52818a7ed6
* Extend fuzzer to generate cases like #53. Currently, the fuzz testcase generator will add at most one fixed-register constraint to an instruction per physical register. This avoids impossible situations, such as specifying that both `v0` and `v1` must be placed into the same `p0`. However, it *should* be possible to say that `v0` is in `p0` before the instruction, and `v1` is in `p0` after the instruction (i.e., at `Early` and `Late` operand positions). This in fact exposes a limitation in the current allocator design: when `v0` is live downward, with the above constraints, it will result in an impossible allocation situation because we cannot split in the middle of an instruction. A subsequent fix will rectify this by using the multi-fixed-reg fixup mechanism. * Handle conflicting Before and After fixed-reg constraints with a copy. This fixes #53. Previously, if two operands on an instruction specified *different* vregs constrained to the same physical register at the Before (Early) and After (Late) points of the instruction, and the Before was live downward as well, we would panic: we can't insert a move into the middle of an instruction, so putting the first vreg in the preg at Early implies we have an unsolveable conflict at Late. We can solve this issue by adding some new logic to insert a copy, and rewrite the constraint. This reuses the multi-fixed-reg-constraint fixup logic. While that logic handles the case where the *same* vreg has multiple *different* fixed-reg constraints, this new logic handles *different* vregs with the *same* fixed-reg constraints, but at different *program points*; so the two are complementary. This addresses the specific test case in #53, and also fuzzes cleanly with the change to the fuzz testcase generator to generate these cases (which also immediately found the bug). * Add a reservation to the PReg when rewriting constraint so it is not doubly-allocated. * Distinguish initial fixup moves from secondary moves. * Use `trace` macro, not `log::trace`, to avoid trace output when feature is disabled. * Rework operand rewriting to properly handle bundle-merging edge case. When the liverange for the defined vreg with fixed constraint at Late is *merged* with the liverange for the used vreg with fixed constraint at Early, the strategy of putting a fixed reservation on the preg at Early fails, because the whole bundle is minimal (if it spans just the instruction's Early and Late and nothing else). This could happen if e.g. the def flows into a blockparam arg that merges with a blockparam defining the used value. Instead we move the def one halfstep earlier, to the Early point, with its fixed-reg constraint still in place. This has the same effect but works when the two are merged. * Fix checker issue: make more flexible in the presence of victim-register saves.
regalloc2: another register allocator
This is a register allocator that started life as, and is about 50% still, a port of IonMonkey's backtracking register allocator to Rust. In many regards, it has been generalized, optimized, and improved since the initial port, and now supports both SSA and non-SSA use-cases.
In addition, it contains substantial amounts of testing infrastructure (fuzzing harnesses and checkers) that does not exist in the original IonMonkey allocator.
See the design overview for (much!) more detail on how the allocator works.
License
This crate is licensed under the Apache 2.0 License with LLVM
Exception. This license text can be found in the file LICENSE.
Parts of the code are derived from regalloc.rs: in particular,
src/checker.rs and src/domtree.rs. This crate has the same license
as regalloc.rs, so the license on these files does not differ.