Commit Graph

170 Commits

Author SHA1 Message Date
Amanieu d'Antras
74928b83fa Replace all assert! with debug_assert!
This results in a ~6% reduction in instruction count.
2022-01-11 03:54:08 +00:00
Amanieu d'Antras
6f59cd407b Use block_insts_and_edits in the checker 2021-12-27 22:09:07 +01:00
Amanieu d'Antras
8ab44c383e Add a helper to iterate over insts and edits of a block in order 2021-12-27 22:08:36 +01:00
Amanieu d'Antras
51493ab03a Apply review feedback 2021-12-12 00:33:30 +00:00
Amanieu d'Antras
38ffc479c2 Simplify the internal representation of PReg 2021-12-11 22:39:19 +00:00
Amanieu d'Antras
870e4729e1 Add fixed stack slots to the fuzzer 2021-12-11 22:39:19 +00:00
Amanieu d'Antras
8f435243e0 Properly handle fixed stack slots during multi-fixed-reg fixup 2021-12-11 22:39:14 +00:00
Amanieu d'Antras
707aacd818 Split up functions in liverange.rs
This helps with profiling even if they are inlined since perf with DWARF
callgraph profiling can attribute execution time to inlined functions.
2021-12-11 22:31:58 +00:00
Amanieu d'Antras
4f8e115115 Refactor requirement computation 2021-12-11 22:31:58 +00:00
Amanieu d'Antras
77e6a9e0d7 Add support for fixed stack slots
This works by allowing a PReg to be marked as being a stack location
instead of a physical register.
2021-12-11 22:31:58 +00:00
Chris Fallin
ef6c8f3226 Fix fuzzbug: add checker metadata for new vreg on multi-fixed-reg fixup move.
When an instruction uses the same vreg constrained to multiple different
fixed registers, the allocator converts all but one of the fixed
constraints to `Any` and then records a special fixup move that copies
the value to the other fixed registers just before the instruction. This
allows the allocator to maintain the invariant that a value lives in
only one place at a time throughout most of its logic, and constrains
the complexity-fallout of this corner case to just a special last-minute
edit.

Unfortunately some recent CPU time thrown at the fuzzer has uncovered
a subtle interaction with the redundant move eliminator that confuses
the checker.

Specifically, when the correct value is *already* in the second
constrained fixed reg, because of an unrelated other move (e.g. because
of a blockparam or other vreg moved from the original), the redundant
move eliminator can delete the fixup move without telling the checker
that it has done so.

Such an optimization is perfectly valid, and the generated code is
correct; but the checker thinks that some other vreg (the one that was
copied from the original) is in the second preg, and panics.

The fix is to use the mechanism that indicates "this move defines a new
vreg" (emitting a `defalloc` checker-instruction) to force the checker
to understand that after the fixup move, the given preg actually
contains the appropriate vreg.
2021-12-04 23:30:30 -08:00
Amanieu d'Antras
6621a57cb7 Fix liveranges for branch parameters 2021-12-01 01:43:20 +00:00
Amanieu d'Antras
0cb3a8019f Rework the API for outgoing blockparams 2021-12-01 01:43:20 +00:00
Chris Fallin
c53fbb4a5c Fix fuzzbug related to bundle priority ordering.
Changes in computation of bundle priorities during review of the initial
PR introduced a possible mis-ordering of priorities: inner-loop bundle
use weights could exceed the weights of 1_000_000 and 2_000_000 used for
minimal bundles without and with fixed uses (respectively). These two
kinds of minimal bundle are meant to be the highest-priority bundles,
evicting any other bundle they need to, because they can't be split
further. This PR introduces two special bundle weights for these two
kinds of bundles, and clamps all other bundle weights to just below
them.

Thanks to @Amanieu for reporting the issue! Fixes #19.
2021-11-30 15:36:12 -08:00
Chris Fallin
c7bc6c941c Merge pull request #15 from cfallin/relicensing
Relicense fully to Apache-2.0 WITH LLVM-exception.
2021-11-18 12:40:54 -08:00
Amanieu d'Antras
a516e6d6f3 Return safepoint_slots as Allocations instead of SpillSlots
This enables us to support reftype vregs in register locations in the
future.
2021-11-16 00:47:43 +00:00
Amanieu d'Antras
a527a6d25a Remove unused clobbers vector 2021-11-16 00:46:05 +00:00
Chris Fallin
cf0d515709 Relicense fully to Apache-2.0 WITH LLVM-exception.
Large parts of the code in regalloc2 are currently licensed under the
Mozilla Public License (MPL) 2.0, because they derive in meaningful
ways from the register allocator in IonMonkey, which is part of
Firefox. The relevant source files are marked as such, with references
to the files in the Firefox source tree.

The intent of the regalloc2 project was to port the register allocator
from Firefox to use in Cranelift, borrowing good technology and
improving on it in the spirit of open source.

However, Several use-cases of Cranelift require, or at least strongly
prefer, the Apache-2.0 license with the LLVM exception (matching the
license of Cranelift itself, and Bytecode Alliance projects
generally). While using this license is not strictly necessary for
regalloc2 to be usable (The MPL is an excellent open-source license!),
relicensing fully under this license to harmonize with the rest of
Cranelift and Bytecode Alliance codebases significantly widens
possibilities and reduces friction; then regalloc2 is "just another
part of Cranelift" and doesn't have to be treated specially.

The source in `src/ion/` specifically began as a fairly direct port of
the algorithms in the following files in the `mozilla-central`
repository (Firefox codebase):

* The bulk of the "backtracking allocator" algorithm:
  * `js/src/jit/BacktrackingAllocator.{cpp,h}`
* Helpers and definitions in the surrounding infrastructure:
  * `js/src/jit/RegisterAllocator.h`
  * `js/src/jit/RegisterAllocator.cpp`
  * `js/src/jit/StackSlotAllocator.h`
  * `js/src/jit/LIR.h`
* A few data structure implementations:
  * `js/src/ds/SplayTree.h`
  * `js/src/ds/PriorityQueue.h`

Subsequent work in improving regalloc2 has caused it to drift from the
direct port -- for example, it no longer uses splay trees or the
direct port of the priority queue above -- but it is of course very
clearly still a derivative work.

Analysis of the contributors to these files indicates that we need
signoff from the following folks:

* Mozilla Corp, for contributions made by Mozilla employees (the
  majority of the code). Communications with Mozilla (thanks
  @tschneidereit and @bholley for doing the work here!) indicate that
  @ekr is able to sign off when ready here.

* Andy Wingo, specifically for the work done in [Bug
  1620197](https://bugzilla.mozilla.org/show_bug.cgi?id=1620197) and
  [Bug 1609057](https://bugzilla.mozilla.org/show_bug.cgi?id=1609057) to
  generalize the stack allocator for a Wasm feature (multiple returns).

Additionally, since the initial port, we have had three contributions
from @Amanieu:
[#9](https://github.com/bytecodealliance/regalloc2/pull/9),
[#11](https://github.com/bytecodealliance/regalloc2/pull/11),
[#13](https://github.com/bytecodealliance/regalloc2/pull/13).

So, if everyone applicable is happy with this relicensing, this PR
removes the MPL-2.0 license in `src/ion/` and marks all files as
covered under `Apache-2.0 WITH LLVM-exception`. Please let us know if
this is OK!

Signoffs:

- [ ] @ekr, for Mozilla's contributions
- [ ] @wingo, for contributions to original code in `mozilla-central`
- [ ] @Amanieu, for the three PRs linked above

Thanks!
2021-11-10 10:54:28 -08:00
Amanieu d'Antras
358c831b31 Remove regs from MachineEnv
It isn't exactly clear what purpose it serves.
2021-09-19 16:40:27 +01:00
Amanieu d'Antras
af527aca88 Fix PReg indexing with >32 pregs 2021-09-19 16:39:56 +01:00
Amanieu d'Antras
9e2ab3d5f7 Address review feedback 2021-09-14 13:12:52 +01:00
Amanieu d'Antras
35ed2109b1 Adjust Operand encoding
The encoding for OperandConstraint is adjusted to free up 2 bits which
allows for 2^21 vregs and 2^6 pregs.
2021-09-13 08:33:17 +01:00
Chris Fallin
ef2c9b3f26 Merge pull request #11 from Amanieu/requirement
Simplify Requirement by removing register classes
2021-09-09 10:37:17 -07:00
Amanieu d'Antras
448f210e32 Simplify Requirement by removing register classes
We never merge bundles from vregs of different classes, so we don't
need to check for register class conflicts.
2021-09-09 11:16:19 +01:00
Amanieu d'Antras
a243c4e575 Remove Function::is_call
The documentation says that this is only used for heuristics, but it
is never actually called. This should be removed for now and perhaps
added back later if we find an actual use for it.
2021-09-09 11:16:11 +01:00
Chris Fallin
6f0893d69d Address review comments. 2021-08-31 17:56:06 -07:00
Chris Fallin
6389071e09 Address review comments. 2021-08-31 17:42:50 -07:00
Chris Fallin
b19fa4857f Rename operand positions to Early and Late, and make weights f16/f32 values. 2021-08-31 17:31:23 -07:00
Chris Fallin
3a18564e98 Addressed more review comments. 2021-08-30 17:51:55 -07:00
Chris Fallin
6d313f2b56 Address review comments: more doc comments and some minor refactorings. 2021-08-30 17:15:37 -07:00
Chris Fallin
e10bffbca8 Fix bug in refactored BitVec (found by @Amanieu). 2021-08-14 13:40:43 -07:00
Chris Fallin
69ad31f013 Replace remaining instances of use of debug feature with debug_assertions.
Also fix some code that did not build in debug mode anymore (d'oh!) in
`src/ion/merges.rs`, as exposed by this change.
2021-08-12 17:35:55 -07:00
Chris Fallin
8ed83e3a57 Fix BitVec::get_or_insert to scan only once. 2021-08-12 15:40:34 -07:00
Chris Fallin
ffc06b2099 Debug output for Operands: omit default/most common positions. 2021-08-12 14:49:42 -07:00
Chris Fallin
c071e44fc0 Derive PartialOrd/Ord/Hash for Operand. 2021-08-12 14:43:13 -07:00
Chris Fallin
eaf8647fdf BitVec: remove zero words to avoid expanding when unnecessary. 2021-08-12 14:40:18 -07:00
Chris Fallin
82b7e6ba7b Review feedback: bitvec: struct-like enum variants, and factor out one-item cache. 2021-08-12 14:33:35 -07:00
Chris Fallin
7652b4b109 Review feedback. 2021-08-12 14:27:20 -07:00
Chris Fallin
2f856435f4 Review feedback. 2021-08-12 14:08:10 -07:00
Chris Fallin
b76b7747d0 Fix comment in postorder.rs. 2021-08-12 14:00:20 -07:00
Chris Fallin
1f30958b5a Improve domtree as per @Amanieu's feedback. 2021-08-12 12:13:56 -07:00
Chris Fallin
3e1e0f39b6 Convert all log::debug to log::trace. 2021-08-12 12:05:19 -07:00
Chris Fallin
84285c26fb Rename OperandPolicy to OperandConstraint as per feedback from @julian-seward1. 2021-08-12 11:17:52 -07:00
Chris Fallin
4c193a9499 Fix heuristic-cost function overflow with high loop depth (found by @Amanieu). 2021-07-28 12:37:32 -07:00
Chris Fallin
66d6821c7b Fix perf issue with many safepoints.
In wasmtime's `gc::many_live_refs` unit-test, approximately ~1K vregs
are live over ~1K safepoints (actually, each vreg is live over half the
safepoints on average, in a LIFO sort of arrangement).

This causes a huge slowdown with the current heuristics. Basically, each
vreg had a `Conflict` requirement because it had both stack uses
(safepoints) and register uses (the actual def and normal use). The
action in this case when processing the vreg's bundle is to split off
the first use -- a conservative-but-correct approach that will always
eventually split bundles far enough to get non-conflicting-requirement
pieces.

However, because each vreg had N stack uses followed by one register
use, this meant that each had to be split N times (!) -- so we had
O(n^2) splits and O(n^2) bundles by the end of the allocation.

This instead implements another simple heuristic that is much better:
when the requirements are conflicting, scan forward and find the exact
point at which the requirements become conflicting, such that the prefix
(first half prior to the split) still has no conflict, and split there.
This turns the above test-case into an O(n)-bundle / O(n)-split
situation.
2021-06-22 14:06:59 -07:00
Chris Fallin
f27abc9c48 Remove infinite-loop check: it is not a high enough bound in some pathological cases (e.g., gc::many_live_refs test in wasmtime), and it has served its purpose in testing. We can rely on more detailed assertions, e.g. that splits actually shrink bundles and that bundles evict only lower-priority bundles, instead. 2021-06-22 12:06:12 -07:00
Chris Fallin
245c212289 Revert "Add fixed-non-allocatable operand support."
This feature needs more thought; for now we will of course continue to
support pinned vregs, but perhaps we can do better for
"pass-through-and-forget" operands that are given non-allocatable
registers.

This reverts commit 736f636c36.
2021-06-20 23:03:44 -07:00
Chris Fallin
22eed0a6ae Make bitvec public; it is used by regalloc.rs shim too. 2021-06-19 12:47:02 -07:00
Chris Fallin
736f636c36 Add fixed-non-allocatable operand support. 2021-06-19 12:17:18 -07:00
Chris Fallin
50eb6fc42f Keep internal modules private, but re-export under fuzzing feature flag 2021-06-19 12:08:37 -07:00