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9556d34a8abc26c8cd5f6158a530fa7bd51cf787
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Author SHA1 Message Date
Alexis Engelke
9556d34a8a fadec: Deprecate address parameter of fd_decode 2020-06-27 19:01:26 +02:00
Alexis Engelke
7333453a19 instrs: Update several operand types and sizes 2020-06-27 19:01:26 +02:00
Alexis Engelke
3221a319d3 instrs: Don't use O-encoding hack for FSTSW 2020-06-27 17:33:58 +02:00
Alexis Engelke
1b5461036e decode: Don't walk escape opcodes in tables 2020-06-27 17:33:58 +02:00
Alexis Engelke
3ad518e22e decode: Store op types early and compact encoding 
* The encoding of operand types in the decode table now only requires 9
  bits instead of the previous 16 bits.
* Operand types are decoded before the operands itself are stored. This
  allows to ignore REX.RB prefixed for specific register types.
 2020-06-27 17:33:58 +02:00
Alexis Engelke
5e1bb1871f decode: Check CR/DR/SEG reg count in ModRM decoder 2020-06-27 17:33:58 +02:00
Alexis Engelke
618d90ed42 instrs: Encode memory size for FPU instructions 2020-06-27 17:33:58 +02:00
Alexis Engelke
bacfecfead fadec: Allow 64-bit decoding on 32-bit platforms 2020-06-27 17:33:58 +02:00
Alexis Engelke
8445060ad9 fadec: Make memory displacement 64-bit large 
While for almost all instructions the memory address displacement is
sign-extended 32-bits (like for immediate operands), there is a single
case where this is not true: the FD/TD mov encoding allows for a 64-bit
memory address to be specified.
 2020-06-25 21:04:10 +02:00
Alexis Engelke
55197817a7 decode: Remove several unneeded #ifdef's 
In many cases, the compiler is able to figure out itself whether support
for one decoding mode is disabled.
 2020-06-25 21:04:10 +02:00
Alexis Engelke
348d1aec4b decode: Minor refactoring for better performance 
This improves decoding performance by ~4%.
 2020-06-25 21:04:10 +02:00
Alexis Engelke
bb4b195dbe instrs/sse,avx: Fix several operand sizes 2020-06-25 21:04:10 +02:00
Alexis Engelke
807d8a817b decode: Change imm_control to get rid of imm_byte 2020-06-19 14:04:17 +02:00
Alexis Engelke
ab5e0c67c1 decode: Don't fall back to memory encoding with 72-table 2020-06-19 14:04:17 +02:00
Alexis Engelke
f978785df3 parseinstrs: Make TrieEntry always hashable 2020-06-17 18:36:18 +02:00
Alexis Engelke
93a61a0ff1 parseinstrs: Remove mnemonic from instr bitstruct 2020-06-17 17:16:53 +02:00
Alexis Engelke
38f52c98b5 parseinstrs: Store mnemonic enum entry in trie 2020-06-17 17:08:23 +02:00
Alexis Engelke
af5b36a58e parseinstrs: Don't needlessly convert to bytes 2020-06-17 16:49:27 +02:00
Alexis Engelke
f4b41a7e80 decode: Use uint16_t for trie 2020-06-17 16:44:22 +02:00
Alexis Engelke
1fedc069b6 parseinstrs: Propagate unpacked data for trie 2020-06-17 16:34:27 +02:00
Alexis Engelke
545ec30ad0 decode: Return partial error on incomplete opcode 2020-06-14 14:01:39 +02:00
Alexis Engelke
8716bd1991 format: Handle offset operands properly 2020-06-14 14:01:14 +02:00
Alexis Engelke
9454f5f746 travis: Remove Travis CI 2020-06-14 13:45:03 +02:00
aengelke
d18b6bb3cf ci: Add CI via GitHub Actions 2020-06-14 13:43:26 +02:00
Alexis Engelke
80ec7ed960 instrs: Fix decoding of XCHG r8, rax 
Opcode 90 is only a NOP if there is no REX.B.
 2020-06-14 13:36:11 +02:00
Alexis Engelke
c3df15e19b api: Store index register in operand struct 
Combined with some reordering of the struct fields, this reduces the
size of an FdInstr from 56 bytes to 48 bytes.
 2020-06-14 13:36:01 +02:00
Alexis Engelke
7a364fcada api: Drop unused internal FD_FLAG_REX 2020-05-17 11:14:52 +02:00
Alexis Engelke
da4cbc237f parseinstr: Use typing.NamedTuple 2020-05-10 14:20:34 +02:00
Alexis Engelke
afc574503f Decode jump targets as offset if address is NULL 
Addresses relative to the actual address of the instruction are decoded
as new offset operand, where the RIP has to be added to obtain the real
value. For backwards compatibility, the new behavior is only exposed if
the address of the instruction is specified as zero.
 2020-03-07 14:30:07 +01:00
Alexis Engelke
dc286b14f2 Unify instruction mnemonics [API break] 
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
 2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb decode: Store CL as register operand for shifts 2020-02-19 16:53:59 +01:00
Alexis Engelke
e65086c76c parseinstr: Separate fields for operand properties 2020-02-16 18:12:07 +01:00
Alexis Engelke
e59117538f parseinstr: Include mnemnonic in flag bitstruct 2020-02-16 18:05:32 +01:00
Alexis Engelke
f538554bb9 Support various smaller instruction set extensions 
In particular: VAESNI, ADX, CLDEMOTE, ENQCMD, PCONFIG, WBNOINVD
 2020-02-10 20:37:07 +01:00
Alexis Engelke
bf5d0ef292 Improve decoding correctness in very rare cases 2020-02-10 20:36:02 +01:00
Alexis Engelke
8572c15973 Handle RVMR encodings correctly in 32-bit mode 
The most significant bit in the immediate is ingored in 32-bit mode.
 2020-02-10 20:34:37 +01:00
Alexis Engelke
f6a66ea4fb Use special root table for VEX 
Some instruction opcodes have an entirely different encoding when a VEX
prefix is present. For example, 0f41 is CMOVNO without mandatory
prefixes while VEX.NP.W0.L1.0f41 is KANDW with a mandatory prefix. To
avoid collisions, the VEX prefix is better handled as a completely
separate decode tree, at the cost of a slight increase in table size.
 2020-02-10 20:34:37 +01:00
Alexis Engelke
b376d0d0f8 parser: Use exceptions instead of assertions 2020-02-10 20:34:37 +01:00
Alexis Engelke
e73dbb3eea Be more restrictive with VSIB encodings 2020-02-10 20:34:37 +01:00
Alexis Engelke
e63fa88da4 Minor fixes (RETF, POPCNT, +PDEP, +PEXT) 2020-02-10 17:17:39 +01:00
Alexis Engelke
889a509a5e Update documentation for latest changes 2019-11-03 11:56:38 +01:00
Alexis Engelke
19b76c809e Add MMX and several other instructions 2019-11-03 11:56:24 +01:00
Alexis Engelke
2bf33017bc Reject invalid move to CS 2019-11-03 11:54:00 +01:00
Alexis Engelke
dbfcf33c33 Add more precise error codes 2019-11-02 22:31:10 +01:00
Alexis Engelke
21c40c48d0 Fix compilation error 2019-11-02 22:18:27 +01:00
Alexis Engelke
c5281e2f58 Add support for several small ISA extensions 2019-11-02 22:17:43 +01:00
Alexis Engelke
7e89bee1f0 Further memory operand annotations 2019-11-02 22:17:20 +01:00
Alexis Engelke
dbf72dd282 Fix VEX+REX handling 2019-11-02 22:16:50 +01:00
Alexis Engelke
a5a15258fd Fix another bug with REX prefix decoding 2019-11-02 21:54:39 +01:00
Alexis Engelke
df4e2725d4 Annotate several more memory-only instructions 2019-11-02 21:50:02 +01:00