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1bd5f7c5729dc02db5bd924c45a198ae46a88608
Commit Graph

99 Commits

Author SHA1 Message Date
Alexis Engelke
1bd5f7c572 decode: Set address size when decoding prefixes 2021-09-20 13:52:06 +02:00
Alexis Engelke
bf0425f057 decode: Expose immediate in RVMR encodings 
The AMD64 instructions VPERMIL2PS and VPERMIL2PD (currently not
supported) encode a fifth immediate operand in the lower bits of the
re-purposed immediate. Expose this value in any case so that no
information gets lost during decoding.
 2021-09-13 17:38:24 +02:00
Alexis Engelke
50f052488d decode: More precise register types 2021-04-02 17:20:23 +02:00
Alexis Engelke
f17d84cee6 format: Emit XACQUIRE/XRELEASE 
As CMPXCHGD has a mandatory prefix table, it is absolutely necessary
that the presence of any tables does not modify any decoding state.
 2021-01-23 14:35:08 +01:00
Alexis Engelke
fe68dbb743 decode: Fix LOCK handling for MOV CR/DR 2021-01-23 14:28:27 +01:00
Alexis Engelke
bd611902b0 parseinstrs: Add separate ModRM indicator to desc 
Some instructions have no ModRM operand and no extended opcode but still
consume a ModRM byte.
 2021-01-23 13:25:23 +01:00
Alexis Engelke
9d7b584121 decode: Verify 3DNow! opcode validity 2021-01-10 18:53:32 +01:00
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
af9188e267 parseinstrs: Respect mem-only/reg-only encodings 2021-01-10 12:02:58 +01:00
Alexis Engelke
d2bf961b77 instrs: Properly handle PUSH/POP of SEG registers 2021-01-03 20:08:34 +01:00
Alexis Engelke
90cce987f0 decode: Remove use of ARCH_* macros 2021-01-02 16:25:25 +01:00
Alexis Engelke
305eb9d568 decode: Inline ModRM decoding 
This is a preparation for further changes to that routine.
 2020-11-29 13:34:16 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
13e7e27640 decode: Minor non-functional changes 2020-11-29 10:03:11 +01:00
Alexis Engelke
8976c7141a decode: Fix erroneous decoding of high-byte regs 2020-11-28 13:54:19 +01:00
Alexis Engelke
757acf18c3 decode: Minor performance improvements 2020-11-27 09:07:52 +01:00
Alexis Engelke
fd80706f54 decode: Store instruction descriptors separately 2020-11-22 22:27:43 +01:00
Alexis Engelke
bb8510d77f decode: Ignore ES/CS/SS/DS override in 64-bit mode 2020-11-22 20:59:13 +01:00
Alexis Engelke
f4215d4260 decode: Remove PrefixSet enum 2020-11-22 16:02:35 +01:00
Alexis Engelke
ad1f1e39c3 decode: Minor non-functional changes 2020-11-22 15:14:57 +01:00
Alexis Engelke
6fe5500444 instrs: Force RIP access to 64-bit and fix XBEGIN 2020-11-22 15:13:52 +01:00
Alexis Engelke
bbc3b34f71 decode: Fix VEX + REX + legacy combinations 2020-11-21 15:43:51 +01:00
Alexis Engelke
7f0bd4de8b decode: Fix combinations of VEX with legacy prefix 2020-11-21 14:59:25 +01:00
Alexis Engelke
318fdc50eb decode: Replace table walk macro with function 2020-11-17 10:43:08 +01:00
Alexis Engelke
58464d6fa1 decode: Fix ignoring VEX.B in 32-bit mode 2020-11-09 09:47:36 +01:00
Alexis Engelke
62b0420147 parseinstr: Simplify opcode naming scheme 2020-11-09 09:47:36 +01:00
Alexis Engelke
9df6ac1788 decode: Replace T8+T72 with T16+T8E for R/M value 2020-11-09 09:47:36 +01:00
Alexis Engelke
01e1587c5c decode: Move prefix before other opcode extensions 2020-11-09 09:47:36 +01:00
Alexis Engelke
2e7e396325 decode: Remove TABLE_PREFIX_REP and use NFx prefix 2020-11-09 09:47:36 +01:00
Alexis Engelke
9b6caeb2ae parseinstrs: Write mnemonics to separate file 2020-07-04 14:35:51 +02:00
Alexis Engelke
c9333ac2c9 instrs: Enforce memory for VSIB encodings 2020-07-04 14:24:59 +02:00
Alexis Engelke
7ee9320840 decode: Add second fixed operand size 2020-06-30 22:07:18 +02:00
Alexis Engelke
1b5461036e decode: Don't walk escape opcodes in tables 2020-06-27 17:33:58 +02:00
Alexis Engelke
3ad518e22e decode: Store op types early and compact encoding 
* The encoding of operand types in the decode table now only requires 9
  bits instead of the previous 16 bits.
* Operand types are decoded before the operands itself are stored. This
  allows to ignore REX.RB prefixed for specific register types.
 2020-06-27 17:33:58 +02:00
Alexis Engelke
5e1bb1871f decode: Check CR/DR/SEG reg count in ModRM decoder 2020-06-27 17:33:58 +02:00
Alexis Engelke
bacfecfead fadec: Allow 64-bit decoding on 32-bit platforms 2020-06-27 17:33:58 +02:00
Alexis Engelke
55197817a7 decode: Remove several unneeded #ifdef's 
In many cases, the compiler is able to figure out itself whether support
for one decoding mode is disabled.
 2020-06-25 21:04:10 +02:00
Alexis Engelke
348d1aec4b decode: Minor refactoring for better performance 
This improves decoding performance by ~4%.
 2020-06-25 21:04:10 +02:00
Alexis Engelke
807d8a817b decode: Change imm_control to get rid of imm_byte 2020-06-19 14:04:17 +02:00
Alexis Engelke
ab5e0c67c1 decode: Don't fall back to memory encoding with 72-table 2020-06-19 14:04:17 +02:00
Alexis Engelke
f4b41a7e80 decode: Use uint16_t for trie 2020-06-17 16:44:22 +02:00
Alexis Engelke
545ec30ad0 decode: Return partial error on incomplete opcode 2020-06-14 14:01:39 +02:00
Alexis Engelke
80ec7ed960 instrs: Fix decoding of XCHG r8, rax 
Opcode 90 is only a NOP if there is no REX.B.
 2020-06-14 13:36:11 +02:00
Alexis Engelke
c3df15e19b api: Store index register in operand struct 
Combined with some reordering of the struct fields, this reduces the
size of an FdInstr from 56 bytes to 48 bytes.
 2020-06-14 13:36:01 +02:00
Alexis Engelke
7a364fcada api: Drop unused internal FD_FLAG_REX 2020-05-17 11:14:52 +02:00
Alexis Engelke
afc574503f Decode jump targets as offset if address is NULL 
Addresses relative to the actual address of the instruction are decoded
as new offset operand, where the RIP has to be added to obtain the real
value. For backwards compatibility, the new behavior is only exposed if
the address of the instruction is specified as zero.
 2020-03-07 14:30:07 +01:00
Alexis Engelke
dc286b14f2 Unify instruction mnemonics [API break] 
It is a longer standing issue that some instructions like ADD, IMUL, and
SHL have multiple mnemonics for different encoding forms. This is a
relict from a time where such information was not stored in the
instruction decoding. This, however, is no longer the case and therefore
the extra mnemonics just increase the number of cases to be handled by
users.
 2020-02-20 10:56:17 +01:00
Alexis Engelke
513a913feb decode: Store CL as register operand for shifts 2020-02-19 16:53:59 +01:00
Alexis Engelke
8572c15973 Handle RVMR encodings correctly in 32-bit mode 
The most significant bit in the immediate is ingored in 32-bit mode.
 2020-02-10 20:34:37 +01:00