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Author SHA1 Message Date
Alexis Engelke
9245a97248 instrs: Add several AMD-only instructions 
- 3DNow! instructions have a trailing immediate byte which indicates the
  opcode. Decoding this with the existing table structure requires more
  effort (in particular, a new lookup table after decoding ModRM would
  be required). Given that AMD even removed 3DNow! over 10 years ago, it
  appears unlikely that this will ever be fully supported. Adding the
  RMI-encoded pseudo-instruction "3DNOW" just to support that opcode.
- FEMMS is a legacy 3DNow! instruction.
- EXTRQ/INSERTQ are instructions with an "unusual" encoding and
  operation mode. This is another instance of 16-bit immediates.
- SVM (AMD's variant of VMX) and SNP instructions are AMD-only.
 2021-01-10 15:18:44 +01:00
Alexis Engelke
51072cac9c format: Generalize ENTER/JMPF/CALLF op. formatting 2021-01-10 15:15:30 +01:00
Alexis Engelke
c050b34ff9 instrs: Add support for undocumented instructions 
Undocumented instruction are not decoded by default.

- SALC: undocumented in any recent manual and unsupported by newer
  Intel CPUs. Including as listed by [1,2].
- Undocumented FPU instructions: see [2].

[1]: http://www.rcollins.org/secrets/opcodes/SALC.html
[2]: https://github.com/xoreaxeaxeax/sandsifter/issues/33
 2021-01-10 15:04:37 +01:00
Alexis Engelke
b8decc8064 instrs: Add AMD encoding of SHL/6 and TEST/1 
- SHL (SAL) encoding with /6: this is not documented by Intel and
  documented by AMD as present, but unsupported by tools.
- TEST encoding with /1: undocumented by Intel, documented by AMD.
 2021-01-10 15:03:23 +01:00
Alexis Engelke
fcb39f5cbe instrs: Add support for AESKL/AESKLE 2021-01-10 14:15:14 +01:00
Alexis Engelke
862b6d285c instrs: Minor operand size fixes 2021-01-10 14:13:44 +01:00
Alexis Engelke
d40ee6db66 instrs: Add FLD and fix FUCOMIP instructions 2021-01-10 14:08:29 +01:00
Alexis Engelke
c87264ace3 instrs: Add MMX PSHUFW instruction 2021-01-10 14:02:39 +01:00
Alexis Engelke
dd4263b169 instrs: Support far jumps/calls encoded target 2021-01-10 12:31:07 +01:00
Alexis Engelke
2f295e5476 instrs: Exact register size for scalar VEX ops 2021-01-10 12:15:49 +01:00
Alexis Engelke
96e513c8ea breaking! instrs: Decode VMOVS[SD] loads correctly 
These instruction ignore the VEX operand if the source operand is a
memory location.

API compatibility: separate handling for different operand types in the
second and third operand (REG+REG vs. MEM+NONE) is needed.
 2021-01-10 12:12:26 +01:00
Alexis Engelke
e86ea540b5 instrs: Fixup register decoding for PEXTR* 2021-01-10 12:11:27 +01:00
Alexis Engelke
a81582cc3a breaking! instrs: Decode MOVLHPS/MOVHLPS 
Now that we support different /r and /m encodings on the same opcode, we
can easily identify MOVLHPS/MOVHLPS as different instructions.

API compatibility: existing code can point the new MOVLHPS/MOVHLPS
mnemonics to the existing handler for MOVHPS/MOVLPS.
 2021-01-10 12:11:27 +01:00
Alexis Engelke
af9188e267 parseinstrs: Respect mem-only/reg-only encodings 2021-01-10 12:02:58 +01:00
Alexis Engelke
111769832f format: Properly output VSIB encodings 2021-01-08 10:37:13 +01:00
Alexis Engelke
018a954b4c encode: Use macro for OPC_SEG mask 2021-01-07 10:20:00 +01:00
Alexis Engelke
dfb28c923d encode: Make internal escape encoding more compact 2021-01-07 10:03:58 +01:00
Alexis Engelke
3fdbd70153 encode: Fix erroneous encoding of high registers 2021-01-07 10:03:17 +01:00
Alexis Engelke
db183ee6f9 meson: Check compiler options and Python version 
Thanks to William Woodruff for pointing out that -Wcast-align=strict is
a GCC-only option, which causes build errors (instead of just
complaining about an unsupported warning option).
 2021-01-05 20:21:44 +01:00
Alexis Engelke
84645afaac README: Add API for encoder 2021-01-03 21:23:24 +01:00
Alexis Engelke
aefab34927 README: Update and include encoder 2021-01-03 21:19:36 +01:00
Alexis Engelke
44808e7b1a format: Format instructions with Intel syntax 2021-01-03 21:18:57 +01:00
Alexis Engelke
d8c7ee94b7 instrs: Minor fixes to operand sizes 2021-01-03 20:08:34 +01:00
Alexis Engelke
d2bf961b77 instrs: Properly handle PUSH/POP of SEG registers 2021-01-03 20:08:34 +01:00
Alexis Engelke
3a3a284f6f parseinstrs: Improve performance 2021-01-03 20:08:34 +01:00
Alexis Engelke
5a77c0e6eb parseinstrs: Use suffix tree to reduce mnem size 
This brings slight size improvements, although due to SSE/MMX
instruction name prefixes, benefits are rather small (~50 bytes).
 2021-01-03 20:08:30 +01:00
Alexis Engelke
e82c9e20db build: Simplify 2021-01-02 16:27:28 +01:00
Alexis Engelke
90cce987f0 decode: Remove use of ARCH_* macros 2021-01-02 16:25:25 +01:00
Alexis Engelke
64a9984fa0 format: Add function fdi_name 2020-12-12 16:24:17 +01:00
Alexis Engelke
305eb9d568 decode: Inline ModRM decoding 
This is a preparation for further changes to that routine.
 2020-11-29 13:34:16 +01:00
Alexis Engelke
aa1a39bd9d instrs: Check SREG validity using modreg table 2020-11-29 11:56:08 +01:00
Alexis Engelke
13e7e27640 decode: Minor non-functional changes 2020-11-29 10:03:11 +01:00
Alexis Engelke
7ab5a18cb0 instrs: Fix naming of some FMA instructions 2020-11-28 13:54:51 +01:00
Alexis Engelke
8976c7141a decode: Fix erroneous decoding of high-byte regs 2020-11-28 13:54:19 +01:00
Alexis Engelke
757acf18c3 decode: Minor performance improvements 2020-11-27 09:07:52 +01:00
Alexis Engelke
fd80706f54 decode: Store instruction descriptors separately 2020-11-22 22:27:43 +01:00
Alexis Engelke
bb8510d77f decode: Ignore ES/CS/SS/DS override in 64-bit mode 2020-11-22 20:59:13 +01:00
Alexis Engelke
8ab9f641b8 instrs: Add TSXLDTRK, AVX_VNNI, HRESET, and UINTR 2020-11-22 17:36:12 +01:00
Alexis Engelke
f4215d4260 decode: Remove PrefixSet enum 2020-11-22 16:02:35 +01:00
Alexis Engelke
ad1f1e39c3 decode: Minor non-functional changes 2020-11-22 15:14:57 +01:00
Alexis Engelke
6fe5500444 instrs: Force RIP access to 64-bit and fix XBEGIN 2020-11-22 15:13:52 +01:00
Alexis Engelke
f9bba6289e instrs: Annotate only-mem and only-reg in opcode 2020-11-22 11:34:55 +01:00
Alexis Engelke
bbc3b34f71 decode: Fix VEX + REX + legacy combinations 2020-11-21 15:43:51 +01:00
Alexis Engelke
7f0bd4de8b decode: Fix combinations of VEX with legacy prefix 2020-11-21 14:59:25 +01:00
Alexis Engelke
318fdc50eb decode: Replace table walk macro with function 2020-11-17 10:43:08 +01:00
Alexis Engelke
95070908d0 tests/decode: Add more test cases 2020-11-09 09:47:36 +01:00
Alexis Engelke
58464d6fa1 decode: Fix ignoring VEX.B in 32-bit mode 2020-11-09 09:47:36 +01:00
Alexis Engelke
62b0420147 parseinstr: Simplify opcode naming scheme 2020-11-09 09:47:36 +01:00
Alexis Engelke
9df6ac1788 decode: Replace T8+T72 with T16+T8E for R/M value 2020-11-09 09:47:36 +01:00
Alexis Engelke
7d7e72746e parseinstr: Split escape and opcode 2020-11-09 09:47:36 +01:00