decode: Group all VSIB handling in single branch
Most instructions don't use VSIB encoding, so move all VSIB-related handling to a single block behind a single branch.
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31
decode.c
31
decode.c
@@ -478,7 +478,6 @@ direct:
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}
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else
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{
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bool vsib = UNLIKELY(DESC_VSIB(desc));
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unsigned dispscale = 0;
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if (UNLIKELY(prefix_evex)) {
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@@ -507,7 +506,7 @@ direct:
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// 16-bit address size implies different ModRM encoding
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if (UNLIKELY(addr_size == 1)) {
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ASSUME(mode == DECODE_32);
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if (vsib) // 16-bit address size + VSIB is UD
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if (UNLIKELY(DESC_VSIB(desc))) // 16-bit addr size + VSIB is UD
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return FD_ERR_UD;
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if (rm < 6)
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op_modrm->misc = rm & 1 ? FD_REG_DI : FD_REG_SI;
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@@ -538,8 +537,7 @@ direct:
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// SIB byte
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uint8_t base = rm;
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if (rm == 4)
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{
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if (rm == 4) {
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if (UNLIKELY(off >= len))
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return FD_ERR_PARTIAL;
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uint8_t sib = buffer[off++];
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@@ -547,22 +545,25 @@ direct:
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unsigned idx = (sib & 0x38) >> 3;
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idx += prefix_rex & PREFIX_REXX ? 8 : 0;
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base = sib & 0x07;
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if (!vsib && idx == 4)
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if (idx == 4)
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idx = FD_REG_NONE;
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if (vsib && prefix_evex) {
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// EVEX.V':EVEX.X:SIB.idx
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idx |= prefix_evex & 0x8 ? 0 : 0x10;
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}
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op_modrm->misc = scale | idx;
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}
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else
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{
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// VSIB must have a memory operand with SIB byte.
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if (vsib)
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return FD_ERR_UD;
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} else {
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op_modrm->misc = FD_REG_NONE;
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}
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if (UNLIKELY(DESC_VSIB(desc))) {
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// VSIB must have a memory operand with SIB byte.
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if (rm != 4)
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return FD_ERR_UD;
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_Static_assert(FD_REG_NONE == 0x3f, "unexpected FD_REG_NONE");
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// idx 4 is valid for VSIB
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if ((op_modrm->misc & 0x3f) == FD_REG_NONE)
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op_modrm->misc &= 0xc4;
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if (prefix_evex) // EVEX.V':EVEX.X:SIB.idx
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op_modrm->misc |= prefix_evex & 0x8 ? 0 : 0x10;
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}
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// RIP-relative addressing only if SIB-byte is absent
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if (op_byte < 0x40 && rm == 5 && mode == DECODE_64)
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op_modrm->reg = FD_REG_IP;
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