cdecc858b4
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
57 lines
1.5 KiB
Plaintext
57 lines
1.5 KiB
Plaintext
test interpret
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test run
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target aarch64
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target s390x
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target x86_64
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target riscv64
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function %fcvt_to_sint(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_sint.i32 v0
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return v1
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}
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; run: %fcvt_to_sint(0x0.0) == 0
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; run: %fcvt_to_sint(0x1.0) == 1
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; run: %fcvt_to_sint(0x1.d6f346p26) == 123456792
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; run: %fcvt_to_sint(0x8.1) == 8
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function %fcvt_to_uint(f32) -> i32 {
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block0(v0:f32):
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v1 = fcvt_to_uint.i32 v0
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return v1
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}
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; run: %fcvt_to_uint(0x0.0) == 0
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; run: %fcvt_to_uint(0x1.0) == 1
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; run: %fcvt_to_uint(0x4.2) == 4
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; run: %fcvt_to_uint(0x4.6) == 4
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; run: %fcvt_to_uint(0x1.d6f346p26) == 123456792
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; run: %fcvt_to_uint(0xB2D05E00.0) == 3000000000
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function %fcvt_to_sint_sat(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_sint_sat.i32 v0
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return v1
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}
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; run: %fcvt_to_sint_sat(0x0.0) == 0
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; run: %fcvt_to_sint_sat(0x1.0) == 1
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; run: %fcvt_to_sint_sat(0x1.d6f346p26) == 123456792
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; run: %fcvt_to_sint_sat(0x8.1) == 8
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; run: %fcvt_to_sint_sat(-0x1.0) == -1
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; run: %fcvt_to_sint_sat(0x1.fffffep127) == 2147483647
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; run: %fcvt_to_sint_sat(-0x1.fffffep127) == -2147483648
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function %fcvt_to_uint_sat(f32) -> i32 {
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block0(v0:f32):
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v1 = fcvt_to_uint_sat.i32 v0
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return v1
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}
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; run: %fcvt_to_uint_sat(0x0.0) == 0
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; run: %fcvt_to_uint_sat(0x1.0) == 1
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; run: %fcvt_to_uint_sat(0x4.2) == 4
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; run: %fcvt_to_uint_sat(0x4.6) == 4
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; run: %fcvt_to_uint_sat(0x1.d6f346p26) == 123456792
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; run: %fcvt_to_uint_sat(0xB2D05E00.0) == 3000000000
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; run: %fcvt_to_uint_sat(-0x1.0) == 0
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; run: %fcvt_to_uint_sat(0x1.fffffep127) == 4294967295
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; run: %fcvt_to_uint_sat(-0x1.fffffep127) == 0
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