* Cranelift: Make `heap_addr` return calculated `base + index + offset`
Rather than return just the `base + index`.
(Note: I've chosen to use the nomenclature "index" for the dynamic operand and
"offset" for the static immediate.)
This move the addition of the `offset` into `heap_addr`, instead of leaving it
for the subsequent memory operation, so that we can Spectre-guard the full
address, and not allow speculative execution to read the first 4GiB of memory.
Before this commit, we were effectively doing
load(spectre_guard(base + index) + offset)
Now we are effectively doing
load(spectre_guard(base + index + offset))
Finally, this also corrects `heap_addr`'s documented semantics to say that it
returns an address that will trap on access if `index + offset + access_size` is
out of bounds for the given heap, rather than saying that the `heap_addr` itself
will trap. This matches the implemented behavior for static memories, and after
https://github.com/bytecodealliance/wasmtime/pull/5190 lands (which is blocked
on this commit) will also match the implemented behavior for dynamic memories.
* Update heap_addr docs
* Factor out `offset + size` to a helper
99 lines
2.7 KiB
Plaintext
99 lines
2.7 KiB
Plaintext
test run
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %load_op_store_iadd_i64(i64 vmctx, i64, i64) -> i64 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i64):
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v3 = heap_addr.i64 heap0, v1, 0, 8
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v4 = iconst.i64 42
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store.i64 v4, v3
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v5 = load.i64 v3
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v6 = iadd.i64 v5, v2
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store.i64 v6, v3
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v7 = load.i64 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_i32(i64 vmctx, i64, i32) -> i32 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i32):
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v3 = heap_addr.i64 heap0, v1, 0, 4
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v4 = iconst.i32 42
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store.i32 v4, v3
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v5 = load.i32 v3
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v6 = iadd.i32 v5, v2
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store.i32 v6, v3
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v7 = load.i32 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_i8(i64 vmctx, i64, i8) -> i8 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i8):
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v3 = heap_addr.i64 heap0, v1, 0, 4
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v4 = iconst.i8 42
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store.i8 v4, v3
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v5 = load.i8 v3
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v6 = iadd.i8 v5, v2
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store.i8 v6, v3
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v7 = load.i8 v3
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return v7
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 1) == 43
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; run: %static_heap_i64_load_store(0, -1) == 41
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function %load_op_store_iadd_isub_iand_ior_ixor_i64(i64 vmctx, i64, i64) -> i64 {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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heap0 = static gv1, min 0x1000, bound 0x1_0000_0000, offset_guard 0, index_type i64
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block0(v0: i64, v1: i64, v2: i64):
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v3 = heap_addr.i64 heap0, v1, 0, 8
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store.i64 v2, v3
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v4 = load.i64 v3
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v5 = iconst.i64 1
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v6 = iadd.i64 v5, v4
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store.i64 v6, v3
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v7 = load.i64 v3
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v8 = iconst.i64 2
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v9 = load.i64 v3
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v10 = isub.i64 v9, v8
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store.i64 v10, v3
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v11 = load.i64 v3
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v12 = iconst.i64 0xf
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v13 = band.i64 v12, v11
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store.i64 v13, v3
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v14 = iconst.i64 0x10
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v15 = load.i64 v3
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v16 = bor.i64 v15, v14
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store.i64 v16, v3
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v17 = load.i64 v3
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v18 = iconst.i64 0xff
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v19 = bxor.i64 v17, v18
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store.i64 v19, v3
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v20 = load.i64 v3
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return v20
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}
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; heap: static, size=0x1000, ptr=vmctx+0, bound=vmctx+8
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; run: %static_heap_i64_load_store(0, 0x1234) == 236
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