Files
wasmtime/cranelift/filetests/filetests/isa/aarch64/simd-comparison-legalize.clif
Trevor Elliott b077854b57 Generate SSA code from returns (#5172)
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
2022-11-08 16:00:49 -08:00

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test compile precise-output
set enable_simd
target aarch64
function %icmp_ne_32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = icmp ne v0, v1
return v2
}
; block0:
; cmeq v3.4s, v0.4s, v1.4s
; mvn v0.16b, v3.16b
; ret
function %icmp_ugt_i32x4(i32x4, i32x4) -> i32x4 {
block0(v0: i32x4, v1: i32x4):
v2 = icmp ugt v0, v1
return v2
}
; block0:
; cmhi v0.4s, v0.4s, v1.4s
; ret
function %icmp_sge_i16x8(i16x8, i16x8) -> i16x8 {
block0(v0: i16x8, v1: i16x8):
v2 = icmp sge v0, v1
return v2
}
; block0:
; cmge v0.8h, v0.8h, v1.8h
; ret
function %icmp_uge_i8x16(i8x16, i8x16) -> i8x16 {
block0(v0: i8x16, v1: i8x16):
v2 = icmp uge v0, v1
return v2
}
; block0:
; cmhs v0.16b, v0.16b, v1.16b
; ret