43a86f14d5
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate. Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
109 lines
3.3 KiB
Rust
109 lines
3.3 KiB
Rust
//! CLI tool to read Cranelift IR files and compile them into native code.
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use crate::disasm::{print_all, PrintRelocs, PrintStackMaps, PrintTraps};
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use crate::utils::{parse_sets_and_triple, read_to_string};
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use anyhow::{Context as _, Result};
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use cranelift_codegen::print_errors::pretty_error;
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use cranelift_codegen::settings::FlagsOrIsa;
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use cranelift_codegen::timing;
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use cranelift_codegen::Context;
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use cranelift_reader::{parse_test, ParseOptions};
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use std::path::Path;
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use std::path::PathBuf;
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use structopt::StructOpt;
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/// Compiles Cranelift IR into target language
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#[derive(StructOpt)]
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pub struct Options {
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/// Print the resulting Cranelift IR
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#[structopt(short("p"))]
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print: bool,
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/// Print pass timing report
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#[structopt(short("T"))]
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report_times: bool,
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/// Print machine code disassembly
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#[structopt(short("D"), long("disasm"))]
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disasm: bool,
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/// Configure Cranelift settings
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#[structopt(long("set"))]
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settings: Vec<String>,
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/// Specify the Cranelift target
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#[structopt(long("target"))]
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target: String,
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/// Specify an input file to be used. Use '-' for stdin.
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#[structopt(parse(from_os_str))]
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files: Vec<PathBuf>,
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/// Enable debug output on stderr/stdout
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#[structopt(short = "d")]
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debug: bool,
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}
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pub fn run(options: &Options) -> Result<()> {
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crate::handle_debug_flag(options.debug);
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let parsed = parse_sets_and_triple(&options.settings, &options.target)?;
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for path in &options.files {
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let name = String::from(path.as_os_str().to_string_lossy());
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handle_module(options, path, &name, parsed.as_fisa())?;
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}
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Ok(())
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}
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fn handle_module(options: &Options, path: &Path, name: &str, fisa: FlagsOrIsa) -> Result<()> {
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let buffer = read_to_string(&path)?;
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let test_file = parse_test(&buffer, ParseOptions::default())
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.with_context(|| format!("failed to parse {}", name))?;
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// If we have an isa from the command-line, use that. Otherwise if the
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// file contains a unique isa, use that.
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let isa = fisa.isa.or(test_file.isa_spec.unique_isa());
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if isa.is_none() {
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anyhow::bail!("compilation requires a target isa");
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};
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for (func, _) in test_file.functions {
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let mut relocs = PrintRelocs::new(options.print);
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let mut traps = PrintTraps::new(options.print);
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let mut stack_maps = PrintStackMaps::new(options.print);
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if let Some(isa) = isa {
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let mut context = Context::new();
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context.func = func;
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let mut mem = vec![];
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// Compile and encode the result to machine code.
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let code_info = context
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.compile_and_emit(isa, &mut mem, &mut relocs, &mut traps, &mut stack_maps)
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.map_err(|err| anyhow::anyhow!("{}", pretty_error(&context.func, err)))?;
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if options.print {
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println!("{}", context.func.display());
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}
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if options.disasm {
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print_all(
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isa,
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&mem,
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code_info.code_size,
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code_info.jumptables_size + code_info.rodata_size,
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&relocs,
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&traps,
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&stack_maps,
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)?;
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}
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}
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}
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if options.report_times {
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print!("{}", timing::take_current());
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}
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Ok(())
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}
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