f636d795c5
* Start adding the load_complex and store_complex instructions. N.b.: The text format is not correct yet. Requires changes to the lexer and parser. I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix. * Get first few encodings of load_complex working. Still needs var args type checking. * Clean up ModRM helper functions in binemit. * Implement 32-bit displace for load_complex * Use encoding helpers instead of doing them all by hand * Initial implementation of store_complex * Parse value list for load/store_complex with + as delimiter. Looks nice. * Add sign/zero-extension and size variants for load_complex. * Add size variants of store_complex. * Add asm helper lines to load/store complex bin tests. * Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation. * Fix Python linting issues * First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now. * Optimization pass now works with all types of loads. * Add store+add -> store_complex to postopt pass * Put complex address optimization behind ISA flag. * Add load/store complex for f32 and f64 * Fixes changes to lexer that broke NaN parsing. Abstracts away the repeated checks for whether or not the characters following a + or - are going to be parsed as a number or not. * Fix formatting issues * Fix register restrictions for complex addresses. * Encoding tests for x86-32. * Add documentation for newly added instructions, recipes, and cdsl changes. * Fix python formatting again * Apply value-list length predicates to all LoadComplex and StoreComplex instructions. * Add predicate types to new encoding helpers for mypy. * Import FieldPredicate to satisfy mypy. * Add and fix some "asm" strings in the encoding tests. * Line-up 'bin' comments in x86/binary64 test * Test parsing of offset-less store_complex instruction. * 'sNaN' not 'sNan' * Bounds check the lookup for polymorphic typevar operand. * Fix encodings for istore16_complex.
96 lines
2.9 KiB
Plaintext
96 lines
2.9 KiB
Plaintext
test postopt
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set is_64bit
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isa x86
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function %dual_loads(i64, i64) -> i64 {
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ebb0(v0: i64, v1: i64):
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[RexOp1rr#8001] v3 = iadd v0, v1
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v4 = load.i64 v3
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v5 = uload8.i64 v3
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v6 = sload8.i64 v3
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v7 = uload16.i64 v3
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v8 = sload16.i64 v3
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v9 = uload32.i64 v3
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v10 = sload32.i64 v3
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[Op1ret#c3] return v10
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}
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; sameln: function %dual_loads
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; nextln: ebb0(v0: i64, v1: i64):
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; nextln: v3 = iadd v0, v1
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; nextln: v4 = load_complex.i64 v0+v1
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; nextln: v5 = uload8_complex.i64 v0+v1
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; nextln: v6 = sload8_complex.i64 v0+v1
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; nextln: v7 = uload16_complex.i64 v0+v1
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; nextln: v8 = sload16_complex.i64 v0+v1
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; nextln: v9 = uload32_complex v0+v1
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; nextln: v10 = sload32_complex v0+v1
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; nextln: return v10
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; nextln: }
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function %dual_loads2(i64, i64) -> i64 {
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ebb0(v0: i64, v1: i64):
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[RexOp1rr#8001] v3 = iadd v0, v1
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v4 = load.i64 v3+1
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v5 = uload8.i64 v3+1
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v6 = sload8.i64 v3+1
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v7 = uload16.i64 v3+1
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v8 = sload16.i64 v3+1
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v9 = uload32.i64 v3+1
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v10 = sload32.i64 v3+1
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[Op1ret#c3] return v10
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}
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; sameln: function %dual_loads2
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; nextln: ebb0(v0: i64, v1: i64):
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; nextln: v3 = iadd v0, v1
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; nextln: v4 = load_complex.i64 v0+v1+1
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; nextln: v5 = uload8_complex.i64 v0+v1+1
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; nextln: v6 = sload8_complex.i64 v0+v1+1
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; nextln: v7 = uload16_complex.i64 v0+v1+1
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; nextln: v8 = sload16_complex.i64 v0+v1+1
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; nextln: v9 = uload32_complex v0+v1+1
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; nextln: v10 = sload32_complex v0+v1+1
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; nextln: return v10
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; nextln: }
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function %dual_stores(i64, i64, i64) {
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ebb0(v0: i64, v1: i64, v2: i64):
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[RexOp1rr#8001] v3 = iadd v0, v1
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[RexOp1st#8089] store.i64 v2, v3
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[RexOp1st#88] istore8.i64 v2, v3
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[RexMp1st#189] istore16.i64 v2, v3
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[RexOp1st#89] istore32.i64 v2, v3
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[Op1ret#c3] return
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}
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; sameln: function %dual_stores
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; nextln: ebb0(v0: i64, v1: i64, v2: i64):
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; nextln: v3 = iadd v0, v1
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; nextln: store_complex v2, v0+v1
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; nextln: istore8_complex v2, v0+v1
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; nextln: istore16_complex v2, v0+v1
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; nextln: istore32_complex v2, v0+v1
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; nextln: return
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; nextln: }
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function %dual_stores2(i64, i64, i64) {
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ebb0(v0: i64, v1: i64, v2: i64):
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[RexOp1rr#8001] v3 = iadd v0, v1
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[RexOp1stDisp8#8089] store.i64 v2, v3+1
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[RexOp1stDisp8#88] istore8.i64 v2, v3+1
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[RexMp1stDisp8#189] istore16.i64 v2, v3+1
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[RexOp1stDisp8#89] istore32.i64 v2, v3+1
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[Op1ret#c3] return
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}
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; sameln: function %dual_stores2
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; nextln: ebb0(v0: i64, v1: i64, v2: i64):
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; nextln: v3 = iadd v0, v1
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; nextln: store_complex v2, v0+v1+1
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; nextln: istore8_complex v2, v0+v1+1
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; nextln: istore16_complex v2, v0+v1+1
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; nextln: istore32_complex v2, v0+v1+1
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; nextln: return
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; nextln: }
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