f6a140a662
This commit adds arm32 code generation for some IR insts. Floating-point instructions are not supported, because regalloc does not allow to represent overlapping register classes, which are needed by VFP/Neon. There is also no support for big-endianness, I64 and I128 types.
61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
test compile
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target arm
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function %icmp(i32, i32) -> b1 {
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block0(v0: i32, v1: i32):
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v2 = icmp eq v0, v1
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return v2
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}
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; check: push {fp, lr}
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; nextln: mov fp, sp
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; nextln: cmp r0, r1
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; nextln: ite eq ; mov r0, #1 ; mov r0, #0
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; nextln: mov sp, fp
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; nextln: pop {fp, lr}
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; nextln: bx lr
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function %ifcmp_trueif(i32, i32) -> b1 {
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block0(v0: i32, v1: i32):
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v2 = ifcmp v0, v1
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v3 = trueif eq v2
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return v3
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}
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; check: push {fp, lr}
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; nextln: mov fp, sp
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; nextln: cmp r0, r1
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; nextln: ite eq ; mov r0, #1 ; mov r0, #0
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; nextln: mov sp, fp
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; nextln: pop {fp, lr}
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; nextln: bx lr
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function %select(i32, i32, i32) -> i32 {
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block0(v0: i32, v1: i32, v2: i32):
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v3 = select v0, v1, v2
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return v3
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}
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; check: push {fp, lr}
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; nextln: mov fp, sp
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; nextln: cmp r0, #0
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; nextln: ite ne ; mov r0, r1 ; mov r0, r2
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; nextln: mov sp, fp
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; nextln: pop {fp, lr}
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; nextln: bx lr
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function %selectif(i32, i32, i32, i32) -> i32 {
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block0(v0: i32, v1: i32, v2: i32, v3: i32):
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v4 = ifcmp v0, v1
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v5 = selectif.i32 eq v4, v2, v3
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return v5
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}
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; check: push {fp, lr}
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; nextln: mov fp, sp
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; nextln: cmp r0, r1
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; nextln: ite eq ; mov r0, r2 ; mov r0, r3
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; nextln: mov sp, fp
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; nextln: pop {fp, lr}
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; nextln: bx lr
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