295 lines
12 KiB
Plaintext
295 lines
12 KiB
Plaintext
; binary emission of 64-bit code.
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test binemit
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set is_64bit
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isa intel
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64.cton | llvm-mc -show-encoding -triple=x86_64
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;
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; Tests for i64 instructions.
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function %I64() {
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fn0 = function %foo()
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sig0 = signature()
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ebb0:
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; Integer Constants.
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; asm: movq $0x01020304f1f2f3f4, %rcx
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[-,%rcx] v1 = iconst.i64 0x0102_0304_f1f2_f3f4 ; bin: 48 b9 01020304f1f2f3f4
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; asm: movq $0x11020304f1f2f3f4, %rsi
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[-,%rsi] v2 = iconst.i64 0x1102_0304_f1f2_f3f4 ; bin: 48 be 11020304f1f2f3f4
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; asm: movq $0x21020304f1f2f3f4, %r10
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[-,%r10] v3 = iconst.i64 0x2102_0304_f1f2_f3f4 ; bin: 49 ba 21020304f1f2f3f4
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; asm: movl $0xff001122, %r8d # 32-bit zero-extended constant.
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[-,%r8] v4 = iconst.i64 0xff00_1122 ; bin: 41 b8 ff001122
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; asm: movq $0xffffffff88001122, %r14 # 32-bit sign-extended constant.
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[-,%r14] v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122
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; Integer Register-Register Operations.
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; asm: addq %rsi, %rcx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 48 01 f1
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; asm: addq %r10, %rsi
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[-,%rsi] v11 = iadd v2, v3 ; bin: 4c 01 d6
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; asm: addq %rcx, %r10
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[-,%r10] v12 = iadd v3, v1 ; bin: 49 01 ca
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; asm: subq %rsi, %rcx
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[-,%rcx] v20 = isub v1, v2 ; bin: 48 29 f1
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; asm: subq %r10, %rsi
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[-,%rsi] v21 = isub v2, v3 ; bin: 4c 29 d6
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; asm: subq %rcx, %r10
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[-,%r10] v22 = isub v3, v1 ; bin: 49 29 ca
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; asm: andq %rsi, %rcx
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[-,%rcx] v30 = band v1, v2 ; bin: 48 21 f1
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; asm: andq %r10, %rsi
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[-,%rsi] v31 = band v2, v3 ; bin: 4c 21 d6
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; asm: andq %rcx, %r10
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[-,%r10] v32 = band v3, v1 ; bin: 49 21 ca
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; asm: orq %rsi, %rcx
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[-,%rcx] v40 = bor v1, v2 ; bin: 48 09 f1
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; asm: orq %r10, %rsi
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[-,%rsi] v41 = bor v2, v3 ; bin: 4c 09 d6
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; asm: orq %rcx, %r10
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[-,%r10] v42 = bor v3, v1 ; bin: 49 09 ca
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; asm: xorq %rsi, %rcx
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[-,%rcx] v50 = bxor v1, v2 ; bin: 48 31 f1
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; asm: xorq %r10, %rsi
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[-,%rsi] v51 = bxor v2, v3 ; bin: 4c 31 d6
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; asm: xorq %rcx, %r10
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[-,%r10] v52 = bxor v3, v1 ; bin: 49 31 ca
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; asm: shlq %cl, %rsi
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[-,%rsi] v60 = ishl v2, v1 ; bin: 48 d3 e6
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; asm: shlq %cl, %r10
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[-,%r10] v61 = ishl v3, v1 ; bin: 49 d3 e2
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; asm: sarq %cl, %rsi
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[-,%rsi] v62 = sshr v2, v1 ; bin: 48 d3 fe
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; asm: sarq %cl, %r10
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[-,%r10] v63 = sshr v3, v1 ; bin: 49 d3 fa
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; asm: shrq %cl, %rsi
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[-,%rsi] v64 = ushr v2, v1 ; bin: 48 d3 ee
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; asm: shrq %cl, %r10
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[-,%r10] v65 = ushr v3, v1 ; bin: 49 d3 ea
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; asm: rolq %cl, %rsi
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[-,%rsi] v66 = rotl v2, v1 ; bin: 48 d3 c6
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; asm: rolq %cl, %r10
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[-,%r10] v67 = rotl v3, v1 ; bin: 49 d3 c2
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; asm: rorq %cl, %rsi
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[-,%rsi] v68 = rotr v2, v1 ; bin: 48 d3 ce
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; asm: rorq %cl, %r10
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[-,%r10] v69 = rotr v3, v1 ; bin: 49 d3 ca
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; Integer Register-Immediate Operations.
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; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits.
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; Some take 8-bit immediates that are sign-extended to 64 bits.
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; asm: addq $-100000, %rcx
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[-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 48 81 c1 fffe7960
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; asm: addq $100000, %rsi
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[-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 48 81 c6 000186a0
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; asm: addq $0x7fffffff, %r10
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[-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 49 81 c2 7fffffff
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; asm: addq $100, %r8
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[-,%r8] v73 = iadd_imm v4, 100 ; bin: 49 83 c0 64
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; asm: addq $-100, %r14
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[-,%r14] v74 = iadd_imm v5, -100 ; bin: 49 83 c6 9c
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; asm: andq $-100000, %rcx
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[-,%rcx] v80 = band_imm v1, -100000 ; bin: 48 81 e1 fffe7960
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; asm: andq $100000, %rsi
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[-,%rsi] v81 = band_imm v2, 100000 ; bin: 48 81 e6 000186a0
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; asm: andq $0x7fffffff, %r10
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[-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 49 81 e2 7fffffff
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; asm: andq $100, %r8
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[-,%r8] v83 = band_imm v4, 100 ; bin: 49 83 e0 64
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; asm: andq $-100, %r14
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[-,%r14] v84 = band_imm v5, -100 ; bin: 49 83 e6 9c
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; asm: orq $-100000, %rcx
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[-,%rcx] v90 = bor_imm v1, -100000 ; bin: 48 81 c9 fffe7960
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; asm: orq $100000, %rsi
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[-,%rsi] v91 = bor_imm v2, 100000 ; bin: 48 81 ce 000186a0
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; asm: orq $0x7fffffff, %r10
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[-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 49 81 ca 7fffffff
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; asm: orq $100, %r8
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[-,%r8] v93 = bor_imm v4, 100 ; bin: 49 83 c8 64
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; asm: orq $-100, %r14
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[-,%r14] v94 = bor_imm v5, -100 ; bin: 49 83 ce 9c
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; asm: ret
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; asm: xorq $-100000, %rcx
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[-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 48 81 f1 fffe7960
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; asm: xorq $100000, %rsi
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[-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 48 81 f6 000186a0
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; asm: xorq $0x7fffffff, %r10
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[-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 49 81 f2 7fffffff
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; asm: xorq $100, %r8
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[-,%r8] v103 = bxor_imm v4, 100 ; bin: 49 83 f0 64
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; asm: xorq $-100, %r14
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[-,%r14] v104 = bxor_imm v5, -100 ; bin: 49 83 f6 9c
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; Register copies.
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; asm: movq %rsi, %rcx
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[-,%rcx] v110 = copy v2 ; bin: 48 89 f1
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; asm: movq %r10, %rsi
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[-,%rsi] v111 = copy v3 ; bin: 4c 89 d6
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; asm: movq %rcx, %r10
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[-,%r10] v112 = copy v1 ; bin: 49 89 ca
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return ; bin: c3
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}
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; Tests for i32 instructions in 64-bit mode.
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;
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; Note that many i32 instructions can be encoded both with and without a REX
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; prefix if they only use the low 8 registers. Here, we are testing the REX
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; encodings which are chosen by default. Switching to non-REX encodings should
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; be done by an instruction shrinking pass.
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function %I32() {
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fn0 = function %foo()
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sig0 = signature()
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ebb0:
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; Integer Constants.
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; asm: movl $0x01020304, %ecx
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[-,%rcx] v1 = iconst.i32 0x0102_0304 ; bin: 40 b9 01020304
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; asm: movl $0x11020304, %esi
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[-,%rsi] v2 = iconst.i32 0x1102_0304 ; bin: 40 be 11020304
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; asm: movl $0x21020304, %r10d
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[-,%r10] v3 = iconst.i32 0x2102_0304 ; bin: 41 ba 21020304
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; asm: movl $0xff001122, %r8d
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[-,%r8] v4 = iconst.i32 0xff00_1122 ; bin: 41 b8 ff001122
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; asm: movl $0x88001122, %r14d
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[-,%r14] v5 = iconst.i32 0xffff_ffff_8800_1122 ; bin: 41 be 88001122
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; Integer Register-Register Operations.
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; asm: addl %esi, %ecx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 40 01 f1
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; asm: addl %r10d, %esi
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[-,%rsi] v11 = iadd v2, v3 ; bin: 44 01 d6
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; asm: addl %ecx, %r10d
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[-,%r10] v12 = iadd v3, v1 ; bin: 41 01 ca
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; asm: subl %esi, %ecx
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[-,%rcx] v20 = isub v1, v2 ; bin: 40 29 f1
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; asm: subl %r10d, %esi
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[-,%rsi] v21 = isub v2, v3 ; bin: 44 29 d6
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; asm: subl %ecx, %r10d
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[-,%r10] v22 = isub v3, v1 ; bin: 41 29 ca
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; asm: andl %esi, %ecx
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[-,%rcx] v30 = band v1, v2 ; bin: 40 21 f1
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; asm: andl %r10d, %esi
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[-,%rsi] v31 = band v2, v3 ; bin: 44 21 d6
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; asm: andl %ecx, %r10d
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[-,%r10] v32 = band v3, v1 ; bin: 41 21 ca
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; asm: orl %esi, %ecx
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[-,%rcx] v40 = bor v1, v2 ; bin: 40 09 f1
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; asm: orl %r10d, %esi
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[-,%rsi] v41 = bor v2, v3 ; bin: 44 09 d6
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; asm: orl %ecx, %r10d
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[-,%r10] v42 = bor v3, v1 ; bin: 41 09 ca
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; asm: xorl %esi, %ecx
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[-,%rcx] v50 = bxor v1, v2 ; bin: 40 31 f1
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; asm: xorl %r10d, %esi
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[-,%rsi] v51 = bxor v2, v3 ; bin: 44 31 d6
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; asm: xorl %ecx, %r10d
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[-,%r10] v52 = bxor v3, v1 ; bin: 41 31 ca
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; asm: shll %cl, %esi
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[-,%rsi] v60 = ishl v2, v1 ; bin: 40 d3 e6
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; asm: shll %cl, %r10d
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[-,%r10] v61 = ishl v3, v1 ; bin: 41 d3 e2
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; asm: sarl %cl, %esi
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[-,%rsi] v62 = sshr v2, v1 ; bin: 40 d3 fe
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; asm: sarl %cl, %r10d
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[-,%r10] v63 = sshr v3, v1 ; bin: 41 d3 fa
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; asm: shrl %cl, %esi
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[-,%rsi] v64 = ushr v2, v1 ; bin: 40 d3 ee
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; asm: shrl %cl, %r10d
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[-,%r10] v65 = ushr v3, v1 ; bin: 41 d3 ea
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; asm: roll %cl, %esi
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[-,%rsi] v66 = rotl v2, v1 ; bin: 40 d3 c6
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; asm: roll %cl, %r10d
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[-,%r10] v67 = rotl v3, v1 ; bin: 41 d3 c2
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; asm: rorl %cl, %esi
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[-,%rsi] v68 = rotr v2, v1 ; bin: 40 d3 ce
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; asm: rorl %cl, %r10d
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[-,%r10] v69 = rotr v3, v1 ; bin: 41 d3 ca
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; Integer Register-Immediate Operations.
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; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits.
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; Some take 8-bit immediates that are sign-extended to 64 bits.
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; asm: addl $-100000, %ecx
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[-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 40 81 c1 fffe7960
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; asm: addl $100000, %esi
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[-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 40 81 c6 000186a0
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; asm: addl $0x7fffffff, %r10d
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[-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 41 81 c2 7fffffff
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; asm: addl $100, %r8d
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[-,%r8] v73 = iadd_imm v4, 100 ; bin: 41 83 c0 64
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; asm: addl $-100, %r14d
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[-,%r14] v74 = iadd_imm v5, -100 ; bin: 41 83 c6 9c
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; asm: andl $-100000, %ecx
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[-,%rcx] v80 = band_imm v1, -100000 ; bin: 40 81 e1 fffe7960
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; asm: andl $100000, %esi
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[-,%rsi] v81 = band_imm v2, 100000 ; bin: 40 81 e6 000186a0
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; asm: andl $0x7fffffff, %r10d
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[-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 41 81 e2 7fffffff
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; asm: andl $100, %r8d
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[-,%r8] v83 = band_imm v4, 100 ; bin: 41 83 e0 64
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; asm: andl $-100, %r14d
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[-,%r14] v84 = band_imm v5, -100 ; bin: 41 83 e6 9c
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; asm: orl $-100000, %ecx
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[-,%rcx] v90 = bor_imm v1, -100000 ; bin: 40 81 c9 fffe7960
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; asm: orl $100000, %esi
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[-,%rsi] v91 = bor_imm v2, 100000 ; bin: 40 81 ce 000186a0
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; asm: orl $0x7fffffff, %r10d
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[-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 41 81 ca 7fffffff
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; asm: orl $100, %r8d
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[-,%r8] v93 = bor_imm v4, 100 ; bin: 41 83 c8 64
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; asm: orl $-100, %r14d
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[-,%r14] v94 = bor_imm v5, -100 ; bin: 41 83 ce 9c
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; asm: ret
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; asm: xorl $-100000, %ecx
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[-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 40 81 f1 fffe7960
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; asm: xorl $100000, %esi
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[-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 40 81 f6 000186a0
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; asm: xorl $0x7fffffff, %r10d
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[-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 41 81 f2 7fffffff
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; asm: xorl $100, %r8d
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[-,%r8] v103 = bxor_imm v4, 100 ; bin: 41 83 f0 64
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; asm: xorl $-100, %r14d
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[-,%r14] v104 = bxor_imm v5, -100 ; bin: 41 83 f6 9c
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; Register copies.
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; asm: movl %esi, %ecx
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[-,%rcx] v110 = copy v2 ; bin: 40 89 f1
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; asm: movl %r10d, %esi
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[-,%rsi] v111 = copy v3 ; bin: 44 89 d6
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; asm: movl %ecx, %r10d
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[-,%r10] v112 = copy v1 ; bin: 41 89 ca
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return ; bin: c3
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}
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