91b1566aca
These tests were only using "test compile" because it doesn't require any filecheck directives to be present, so just stop requiring filecheck directives for "test regalloc" and other filecheck-based test drivers.
40 lines
918 B
Plaintext
40 lines
918 B
Plaintext
test regalloc
|
|
isa intel haswell
|
|
|
|
function %pr165() native {
|
|
ebb0:
|
|
v0 = iconst.i32 0x0102_0304
|
|
v1 = iconst.i32 0x1102_0304
|
|
v2 = iconst.i32 0x2102_0304
|
|
v20 = ishl v1, v0
|
|
v21 = ishl v2, v0
|
|
v22 = sshr v1, v0
|
|
v23 = sshr v2, v0
|
|
v24 = ushr v1, v0
|
|
v25 = ushr v2, v0
|
|
istore8 v0, v1+0x2710
|
|
istore8 v1, v0+0x2710
|
|
return
|
|
}
|
|
|
|
; Same as above, but use so many registers that spilling is required.
|
|
; Note: This is also a candidate for using xchg instructions.
|
|
function %emergency_spill() native {
|
|
ebb0:
|
|
v0 = iconst.i32 0x0102_0304
|
|
v1 = iconst.i32 0x1102_0304
|
|
v2 = iconst.i32 0x2102_0304
|
|
v3 = iconst.i32 0x3102_0304
|
|
v4 = iconst.i32 0x4102_0304
|
|
v20 = ishl v1, v0
|
|
v21 = ishl v2, v3
|
|
v22 = sshr v1, v0
|
|
v23 = sshr v2, v0
|
|
v24 = ushr v1, v0
|
|
v25 = ushr v2, v0
|
|
istore8 v0, v1+0x2710
|
|
istore8 v1, v0+0x2710
|
|
istore8 v3, v4+0x2710
|
|
return
|
|
}
|