Files
wasmtime/cranelift/filetests/filetests/isa/riscv64/condops.clif
Trevor Elliott f04decc4a1 Use capstone to validate precise-output tests (#5780)
Use the capstone library to disassemble precise-output tests, in addition to pretty-printing their vcode.
2023-02-15 16:35:10 -08:00

153 lines
2.4 KiB
Plaintext

test compile precise-output
set unwind_info=false
target riscv64
function %f(i8, i64, i64) -> i64 {
block0(v0: i8, v1: i64, v2: i64):
v3 = iconst.i8 42
v4 = icmp eq v0, v3
v5 = select.i64 v4, v1, v2
return v5
}
; VCode:
; block0:
; andi a3,a0,255
; li a4,42
; andi a5,a4,255
; select_reg a0,a1,a2##condition=(a3 eq a5)
; ret
;
; Disassembled:
; block0: ; offset 0x0
; andi a3, a0, 0xff
; addi a4, zero, 0x2a
; andi a5, a4, 0xff
; beq a3, a5, 0xc
; ori a0, a2, 0
; j 8
; ori a0, a1, 0
; ret
function %g(i8) -> i8 {
block0(v0: i8):
v3 = iconst.i8 42
v4 = icmp eq v0, v3
return v4
}
; VCode:
; block0:
; li t2,42
; uext.b a1,a0
; uext.b a3,t2
; eq a0,a1,a3##ty=i8
; ret
;
; Disassembled:
; block0: ; offset 0x0
; addi t2, zero, 0x2a
; andi a1, a0, 0xff
; andi a3, t2, 0xff
; bne a1, a3, 0xc
; addi a0, zero, 1
; j 8
; mv a0, zero
; ret
function %h(i8, i8, i8) -> i8 {
block0(v0: i8, v1: i8, v2: i8):
v3 = bitselect.i8 v0, v1, v2
return v3
}
; VCode:
; block0:
; and a1,a0,a1
; not a3,a0
; and a5,a3,a2
; or a0,a1,a5
; ret
;
; Disassembled:
; block0: ; offset 0x0
; and a1, a0, a1
; not a3, a0
; and a5, a3, a2
; or a0, a1, a5
; ret
function %i(i8, i8, i8) -> i8 {
block0(v0: i8, v1: i8, v2: i8):
v3 = select.i8 v0, v1, v2
return v3
}
; VCode:
; block0:
; andi a3,a0,255
; select_i8 a0,a1,a2##condition=a3
; ret
;
; Disassembled:
; block0: ; offset 0x0
; andi a3, a0, 0xff
; beqz a3, 0xc
; ori a0, a1, 0
; j 8
; ori a0, a2, 0
; ret
function %i(i32, i8, i8) -> i8 {
block0(v0: i32, v1: i8, v2: i8):
v3 = iconst.i32 42
v4 = icmp.i32 eq v0, v3
v5 = select.i8 v4, v1, v2
return v5
}
; VCode:
; block0:
; addiw a3,a0,0
; li a4,42
; addiw a5,a4,0
; select_reg a0,a1,a2##condition=(a3 eq a5)
; ret
;
; Disassembled:
; block0: ; offset 0x0
; sext.w a3, a0
; addi a4, zero, 0x2a
; sext.w a5, a4
; beq a3, a5, 0xc
; ori a0, a2, 0
; j 8
; ori a0, a1, 0
; ret
function %i128_select(i8, i128, i128) -> i128 {
block0(v0: i8, v1: i128, v2: i128):
v3 = select.i128 v0, v1, v2
return v3
}
; VCode:
; block0:
; mv a7,a1
; andi a5,a0,255
; select_i128 [a0,a1],[a7,a2],[a3,a4]##condition=a5
; ret
;
; Disassembled:
; block0: ; offset 0x0
; ori a7, a1, 0
; andi a5, a0, 0xff
; beqz a5, 0x10
; ori a0, a7, 0
; ori a1, a2, 0
; j 0xc
; ori a0, a3, 0
; ori a1, a4, 0
; ret