* cranelift: Enable more SIMD tests * cranelift: Reorganize icmp tests * cranelift: Enable SIMD icmp tests for unsigned ops * cranelift: Cleanup trailing newlines
61 lines
1.3 KiB
Plaintext
61 lines
1.3 KiB
Plaintext
test run
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target aarch64
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target s390x
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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function %fcmp_eq_f32x4() -> i8 {
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block0:
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v0 = vconst.f32x4 [0.0 -0x4.2 0x0.33333 -0.0]
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v1 = vconst.f32x4 [0.0 -0x4.2 0x0.33333 -0.0]
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v2 = fcmp eq v0, v1
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v8 = vall_true v2
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return v8
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}
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; run: %fcmp_eq_f32x4() == 1
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function %fcmp_lt_f32x4() -> i8 {
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block0:
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v0 = vconst.f32x4 [0.0 -0x4.2 0x0.0 -0.0]
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v1 = vconst.f32x4 [0x0.001 0x4.2 0x0.33333 0x1.0]
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v2 = fcmp lt v0, v1
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v8 = vall_true v2
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return v8
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}
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; run: %fcmp_lt_f32x4() == 1
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function %fcmp_ge_f64x2() -> i8 {
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block0:
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v0 = vconst.f64x2 [0x0.0 0x4.2]
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v1 = vconst.f64x2 [0.0 0x4.1]
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v2 = fcmp ge v0, v1
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v8 = vall_true v2
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return v8
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}
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; run: %fcmp_ge_f64x2() == 1
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function %fcmp_uno_f64x2() -> i8 {
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block0:
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v0 = vconst.f64x2 [0.0 NaN]
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v1 = vconst.f64x2 [NaN 0x4.1]
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v2 = fcmp uno v0, v1
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v8 = vall_true v2
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return v8
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}
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; run: %fcmp_uno_f64x2() == 1
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function %fcmp_gt_nans_f32x4() -> i8 {
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block0:
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v0 = vconst.f32x4 [NaN 0x42.0 -NaN NaN]
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v1 = vconst.f32x4 [NaN NaN 0x42.0 Inf]
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v2 = fcmp gt v0, v1
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; now check that the result v2 is all zeroes
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v3 = vconst.i32x4 0x00
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v4 = bitcast.i32x4 v2
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v5 = icmp eq v3, v4
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v8 = vall_true v5
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return v8
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}
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; run: %fcmp_gt_nans_f32x4() == 1
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