edae6c0217
* x64: Add non-SSE4.1 lowerings of `pmov{s,z}x*`
This commit adds lowerings for a suite of sign/zero extension
instructions which don't require SSE4.1. Like before these lowerings are
based on LLVM's output.
This commit also deletes special casees for `i16x8.extmul_{low,high}_*`
since the output of the special case is the same as the default lowering
of all the component instructions used within as well.
* Remove SSE4.1 specialization of `uwiden_high`
LLVM prefers the `punpckh*`-based lowerings and at least according to
`llvm-mca` these are slightly better cycle-wise too.
323 lines
5.1 KiB
Plaintext
323 lines
5.1 KiB
Plaintext
test compile precise-output
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target x86_64
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function %f1(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = swiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovsxbw %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovsxbw %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f2(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = swiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovsxwd %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovsxwd %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f3(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = swiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovsxdq %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovsxdq %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f4(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = swiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm0, %xmm2
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; palignr $8, %xmm2, %xmm0, %xmm2
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; pmovsxbw %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqa %xmm0, %xmm2
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; palignr $8, %xmm0, %xmm2
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; pmovsxbw %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f5(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = swiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; movdqa %xmm0, %xmm2
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; palignr $8, %xmm2, %xmm0, %xmm2
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; pmovsxwd %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; movdqa %xmm0, %xmm2
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; palignr $8, %xmm0, %xmm2
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; pmovsxwd %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f6(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = swiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pshufd $238, %xmm0, %xmm2
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; pmovsxdq %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pshufd $0xee, %xmm0, %xmm2
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; pmovsxdq %xmm2, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f7(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = uwiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovzxbw %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovzxbw %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f8(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = uwiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovzxwd %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovzxwd %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f9(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = uwiden_low v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; pmovzxdq %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pmovzxdq %xmm0, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f10(i8x16) -> i16x8 {
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block0(v0: i8x16):
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v1 = uwiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm3
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; pxor %xmm3, %xmm3, %xmm3
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; punpckhbw %xmm0, %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pxor %xmm3, %xmm3
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; punpckhbw %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f11(i16x8) -> i32x4 {
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block0(v0: i16x8):
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v1 = uwiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm3
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; pxor %xmm3, %xmm3, %xmm3
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; punpckhwd %xmm0, %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; pxor %xmm3, %xmm3
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; punpckhwd %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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function %f12(i32x4) -> i64x2 {
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block0(v0: i32x4):
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v1 = uwiden_high v0
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return v1
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}
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; VCode:
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; pushq %rbp
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; movq %rsp, %rbp
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; block0:
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; uninit %xmm3
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; xorps %xmm3, %xmm3, %xmm3
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; unpckhps %xmm0, %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; pushq %rbp
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; movq %rsp, %rbp
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; block1: ; offset 0x4
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; xorps %xmm3, %xmm3
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; unpckhps %xmm3, %xmm0
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; movq %rbp, %rsp
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; popq %rbp
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; retq
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